Letícia Maria Veiras Bolzani

发表

An integrated approach for increasing the soft-error detection capabilities in SoCs processors

Paolo Bernardi, Massimo Violante, Maurizio Rebaudengo, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores

Giovanni Squillero, Ernesto Sánchez, Massimiliano Schillaci, 2007, GECCO '07.

Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores

Giovanni Squillero, Ernesto Sánchez, Massimiliano Schillaci, 2007, 2007 IEEE Congress on Evolutionary Computation.

Extended Fault Detection Techniques for Systems-on-Chip

Paolo Bernardi, Matteo Sonza Reorda, Letícia Maria Veiras Bolzani, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Hierarchical identification of NBTI-critical gates in nanoscale logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2014, 2014 15th Latin American Test Workshop - LATW.

Analyzing NBTI impact on SRAMs with resistive-open defects

Fabian Vargas, Letícia Maria Veiras Bolzani, Thiago Copetti, 2016, 2016 17th Latin-American Test Symposium (LATS).

A Hybrid Approach to Fault Detection and Correction in SoCs

Paolo Bernardi, Matteo Sonza Reorda, Letícia Maria Veiras Bolzani, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

A Test Platform for Dependability Analysis of SoCs Exposed to EMI and Radiation

Ariel Lutenberg, Fabian Vargas, Fernando Hernandez, 2012, J. Electron. Test..

An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems

Fabian Vargas, Letícia Maria Veiras Bolzani, Dhiego Silva, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

Message from the LATS2015 Chairs

Yervant Zorian, Vishwani D. Agrawal, Víctor H. Champac, 2015, LATS.

Analyzing the behavior of FinFET SRAMs with resistive defects

Tiago R. Balen, Letícia Maria Veiras Bolzani, Thiago Copetti, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Selected Peer Reviewed Articles from the 17th "IEEE Latin-American Test Symposium, " Foz do Iguaçu, Brazil, April 6-8, 2016

Letícia Maria Veiras Bolzani, 2016, J. Low Power Electron..

Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013

Matteo Sonza Reorda, Letícia Maria Veiras Bolzani, 2014, J. Low Power Electron..

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations

Fabian Vargas, Víctor H. Champac, Letícia Maria Veiras Bolzani, 2016, Microelectron. Reliab..

Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs

Enrico Macii, Andrea Calimera, Letícia Maria Veiras Bolzani, 2015, 2015 28th International Conference on VLSI Design.

Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs

Tiago R. Balen, Letícia Maria Veiras Bolzani, Thiago Copetti, 2017, VLSI-SoC.

A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems

Fabian Vargas, Letícia Maria Veiras Bolzani, Dhiego Silva, 2011, 2011 Sixteenth IEEE European Test Symposium.

Introducing SW-based fault handling mechanisms to cope with EMI in embedded electronics: are they a good remedy?

Fabian Vargas, Matteo Sonza Reorda, Letícia Maria Veiras Bolzani, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores

Giovanni Squillero, Matteo Sonza Reorda, Ernesto Sánchez, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach

Fabian Vargas, Mario García-Valderas, Luis Entrena, 2012, J. Electron. Test..

NBTI-aware design of integrated circuits: a hardware-based approach

Fabian Vargas, Letícia Maria Veiras Bolzani, Thiago Copetti, 2015, 2015 16th Latin-American Test Symposium (LATS).

An efficient EDAC approach for handling multiple bit upsets in memory array

Fabian Vargas, Letícia Maria Veiras Bolzani, Eduardo Augusto Bezerra, 2018, Microelectron. Reliab..

Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs

Fabian Vargas, Enrico Macii, Andrea Calimera, 2013, 2013 14th Latin American Test Workshop - LATW.

On-line detection of control-flow errors in SoCs by means of an infrastructure IP core

Fabian Vargas, Paolo Bernardi, Massimo Violante, 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

A new hybrid fault detection technique for systems-on-a-chip

Fabian Vargas, Paolo Bernardi, Massimo Violante, 2006, IEEE Transactions on Computers.

Modeling of Physical Defects in PN Junction Based Graphene Devices

Enrico Macii, Massimo Poncino, Andrea Calimera, 2014, J. Electron. Test..

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

Fabian Vargas, Giovanni Squillero, Jaan Raik, 2015, 2015 16th Latin-American Test Symposium (LATS).

Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits

Enrico Macii, Massimo Poncino, Alberto Macii, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Reliability analysis of an on-chip watchdog for embedded systems exposed to radiation and EMI

Ariel Lutenberg, Letícia Maria Veiras Bolzani, Fabian Vargas, 2013, 2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo).

Placement-aware clustering for integrated clock and power gating

Enrico Macii, Massimo Poncino, Alberto Macii, 2009, 2009 IEEE International Symposium on Circuits and Systems.

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems

Fabian Vargas, Letícia Maria Veiras Bolzani, Jimmy Tarrillo, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Fabian Vargas, Said Hamdioui, Mottaqiallah Taouil, 2018, Microelectron. Reliab..

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

Fabian Vargas, Letícia Maria Veiras Bolzani, Thiago Copetti, 2012, 2012 13th Latin American Test Workshop (LATW).

Identifying NBTI-Critical Paths in Nanoscale Logic

Fabian Vargas, Raimund Ubar, Jaan Raik, 2013, 2013 Euromicro Conference on Digital System Design.

Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects

Fabian Vargas, Letícia Maria Veiras Bolzani, G. Cardoso Medeiros, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Enabling concurrent clock and power gating in an industrial design flow

Enrico Macii, Massimo Poncino, Alberto Macii, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

A software-based methodology for the generation of peripheral test sets based on high-level descriptions

Matteo Sonza Reorda, Ernesto Sánchez, Letícia Maria Veiras Bolzani, 2007, SBCCI '07.

Integrating embedded test infrastructure in SRAM cores to detect aging

Yervant Zorian, Fabian Vargas, Gurgen Harutunyan, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

A Hybrid Approach for Detection and Correction of Transient Faults in SoCs

Paolo Bernardi, Matteo Sonza Reorda, Letícia Maria Veiras Bolzani, 2010, IEEE Transactions on Dependable and Secure Computing.

12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011

Yervant Zorian, Fabian Vargas, Fernanda Gusmão de Lima Kastensmidt, 2011, J. Low Power Electron..

An optimized hybrid approach to provide fault detection and correction in SoCs

Paolo Bernardi, Matteo Sonza Reorda, Letícia Maria Veiras Bolzani, 2007, SBCCI '07.

Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications

Paolo Bernardi, Massimo Violante, Matteo Sonza Reorda, 2006, Seventh International Workshop on Microprocessor Test and Verification (MTV'06).

Investigating the Use of BICS to detect resistive-open defects in SRAMs

João Paulo Teixeira, Isabel C. Teixeira, Letícia Maria Veiras Bolzani, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices

Enrico Macii, Massimo Poncino, Andrea Calimera, 2013, 2013 14th Latin American Test Workshop - LATW.

Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments

Fabian Vargas, Alex R. Pinto, Carlos Barros Montez, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

Fabian Vargas, Massimo Violante, Maurizio Rebaudengo, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

An On-Chip Sensor to Monitor NBTI Effects in SRAMs

Fabian Vargas, Letícia Maria Veiras Bolzani, Thiago Copetti, 2014, J. Electron. Test..

Review of Manufacturing Process Defects and Their Effects on Memristive Devices

Said Hamdioui, Stephan Menzel, Letícia Maria Veiras Bolzani, 2021, Journal of Electronic Testing.

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

Tiago R. Balen, Said Hamdioui, Mottaqiallah Taouil, 2021, J. Electron. Test..

Evaluating the Impact of Process Variation on RRAMs

Fabian Vargas, Said Hamdioui, Letícia Maria Veiras Bolzani, 2021, 2021 IEEE 22nd Latin American Test Symposium (LATS).