Hsiang-Hui Chang

发表

A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS

Shang-Ming Lee, Hsiang-Hui Chang, Chao-Wen Chou, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A shifted-averaging VCO with precise multiphase outputs and low jitter operation

Shen-Iuan Liu, Hsiang-Hui Chang, Shang-Ping Chen, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A spread-spectrum clock generator with triangular modulation

Shen-Iuan Liu, Hsiang-Hui Chang, I-Hui Hua, 2003 .

A Low-Current Digitally Predistorted Direct-Conversion Transmitter With 25% Duty-Cycle Passive Mixer

Hsiang-Hui Chang, Manel Collados, Bernard Tenbroek, 2014, IEEE Transactions on Microwave Theory and Techniques.

A fractional spur reduction technique for RF TDC-based all digital PLLs

Ping-Ying Wang, Hsiang-Hui Chang, J.-H.C. Zhan, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

A 65nm GSM/GPRS/EDGE SoC with Integrated BT/FM

Hsiang-Hui Chang, Tzung-Han Wu, Hung-Chieh Tsai, 2012, RFIC 2012.

Low jitter Butterworth delay-locked loops

Shen-Iuan Liu, Hsiang-Hui Chang, Chih-Hao Sun, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A fast locking and low jitter delay-locked loop using DHDL

Shen-Iuan Liu, Hsiang-Hui Chang, Jyh-Woei Lin, 2003 .

A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM

Hsiang-Hui Chang, Tzung-Han Wu, Hung-Chieh Tsai, 2012, IEEE Journal of Solid-State Circuits.

A HSPA+/WCDMA/EDGE 40nm Modem SoC with embedded RF transceiver supporting RX diversity

Hsiang-Hui Chang, Jon Strange, David Ivory, 2014, 2014 IEEE Radio Frequency Integrated Circuits Symposium.

FM Radio Receiver

Hsiang-Hui Chang, Tsung-Yao Lin, Chieh-Hung Chen, 2006 .

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability

Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

Ping-Ying Wang, Hsiang-Hui Chang, J.-H.C. Zhan, 2009, IEEE Journal of Solid-State Circuits.

A low-current digitally predistorted 3G-4G transmitter in 40nm CMOS

Hsiang-Hui Chang, Manel Collados, Bernard Tenbroek, 2013, 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

Shen-Iuan Liu, Jung-Yu Chang, Hsiang-Hui Chang, 2006 .

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE

Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A Calibrated Pulse Generator for Impuljse-radio UWB Applications

Shen-Iuan Liu, Hsiang-Hui Chang, Che-Fu Liang, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

Rong-Jyi Yang, Shen-Iuan Liu, Hsiang-Hui Chang, 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC

Hsiang-Hui Chang, Tzung-Han Wu, George Chien, 2011, IEEE Journal of Solid-State Circuits.

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

Shen-Iuan Liu, Hsiang-Hui Chang, 2005 .

A 320fs-RMS-jitter and 300kHz-BW all-digital fractional-N PLL with self-corrected TDC and fast temperature tacking loop for WiMax/WLAN 11n

Hsiang-Hui Chang, Chia-Huang Fu, Monty Chiu, 2009, 2009 Symposium on VLSI Circuits.

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS

Hsiang-Hui Chang, Lan-Chou Cho, Augusto Marques, 2011, IEEE Asian Solid-State Circuits Conference 2011.

A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL

Shen-Iuan Liu, Hsiang-Hui Chang, Chih-Hao Sun, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 10-mA Current and 1.1-μV Sensitivity Single-Chip FM Radio Receiver

Hsiang-Hui Chang, Tsong-Lin Lee, Tsung-Yao Lin, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

A wide-range and fixed latency of one clock cycle delay-locked loop

Hsiang-Hui Chang, Shen-Iuan Liu, Jyh-Woei Lin, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A transfer-curve-folded DCO in 0.13μm CMOS

Ping-Ying Wang, Hsiang-Hui Chang, J.-H.C. Zhan, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture

Shen-Iuan Liu, Hsiang-Hui Chang, Kuang-Wei Cheng, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.