Morteza Saheb Zamani

发表

Early Buffer Planning with Congestion Control Using Buffer Requirement Map

Ali Jahanian, Morteza Saheb Zamani, 2010, J. Circuits Syst. Comput..

Reducing inter-configuration memory usage and performance improvement in reconfigurable computing systems

Morteza Saheb Zamani, Farhad Mehdipour, Mehdi Sedighi, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Auxiliary qubit selection: a physical synthesis technique for quantum circuits

Morteza Saheb Zamani, Mehdi Sedighi, Naser MohammadZadeh, 2011, Quantum Inf. Process..

RECONFIGURABLE COMPUTING SYSTEMS

Mohammad Reza Meybodi, Morteza Saheb Zamani, Farhad Mehdipour, 2003 .

Quantum-Logic Synthesis of Hermitian Gates

Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh, 2015, ACM J. Emerg. Technol. Comput. Syst..

Performance Enhancement of an Adaptive Dynamic Extensible Processor by Using a Heterogeneous Reconfigurable Functional Unit

Morteza Saheb Zamani, Farhad Mehdipour, Behnam Ghavami, 2007 .

A system architecture for parallel analysis of flux-balanced metabolic pathways

Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh, 2018, Comput. Biol. Chem..

Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins

Morteza Saheb Zamani, Somayeh Kashi, 2012, 2012 15th Euromicro Conference on Digital System Design.

Neutralizing a design-for-hardware-trust technique

Morteza Saheb Zamani, Seyed Mohammad Hossein Shekarian, Shirin Alami, 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

Using metro-on-chip in physical design flow for congestion and routability improvement

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2008, Microelectron. J..

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

Morteza Saheb Zamani, Naser MohammadZadeh, Ali Jahanian, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Block-based quantum-logic synthesis

Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh, 2010, Quantum Inf. Comput..

Prediction and reduction of routing congestion

Morteza Saheb Zamani, Ali Jahanian, Mehdi Saeedi, 2006, ISPD '06.

Rule-based optimization of reversible circuits

Morteza Saheb Zamani, Mona Arabzadeh, Mehdi Saeedi, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

A library-based synthesis methodology for reversible logic pdf

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2010, Microelectron. J..

A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs

Morteza Saheb Zamani, Hamid R. Zarandi, Hassan Ebrahimi, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems

Morteza Saheb Zamani, Farhad Mehdipour, Mehdi Sedighi, 2006, Microprocess. Microsystems.

Reversible circuit synthesis using a cycle-based approach pdf

Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian, 2010, JETC.

One-way quantum computer simulation

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2015, Microprocess. Microsystems.

Improved performance and yield with chip master planning design methodology

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2009, GLSVLSI '09.

Aging Mitigation in FPGAs Considering Delay, Power, and Temperature

Morteza Saheb Zamani, Mohammad Hadi Mottaghi, Mehdi Sedighi, 2020, IEEE Transactions on Reliability.

A Novel Crosstalk Estimator after Placement

Morteza Saheb Zamani, Arash Mehdizadeh, 2008 .

Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework

Morteza Saheb Zamani, Kazuaki Murakami, Farhad Mehdipour, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

FogLight: an efficient matrix-based approach to construct metabolic pathways by search space reduction

Morteza Saheb Zamani, Mehrshad Khosraviani, Gholamreza Bidkhori, 2016, Bioinform..

A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs

Morteza Saheb Zamani, Hassan Ebrahimi, Seyyed Ahmad Razavi, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

A reconfigurable architecture for implementing multiple cipher algorithms

Morteza Saheb Zamani, Farhad Mehdipour, Babak Sadeghian, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty

Morteza Saheb Zamani, Mehdi Saeedi, Maryam Taajobian, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication

Morteza Saheb Zamani, M. S. Zamani, S. A. Razavi, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Performance and Timing Yield Enhancement using Highway-on-Chip Planning

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

FPGA-Based Circuit Model Emulation of Quantum Algorithms

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm

Morteza Saheb Zamani, Minoo Mirsaeedi, Mehdi Saeedi, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Optimization of One-Way Quantum Computation Measurement Patterns

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2017, International Journal of Theoretical Physics.

A cycle-based synthesis algorithm for reversible logic

Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian, 2009, 2009 Asia and South Pacific Design Automation Conference.

GA-based approach to find the stabilizers of a given sub-space

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2014, Genetic Programming and Evolvable Machines.

OWQS: One-Way Quantum Computation Simulator

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2012, 2012 15th Euromicro Conference on Digital System Design.

Simultaneous improvement of area, delay, and fault tolerance in quantum circuits

Morteza Saheb Zamani, Mehdi Sedighi, Zahra Nabizadeh, 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

Reduction of process variation effect on FPGAs using multiple configurations

Morteza Saheb Zamani, Mahdi Nabiyouni, Delasa Aghamirzaie, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

An efficient net ordering algorithm for buffer insertion

Morteza Saheb Zamani, Hamid Reza Kheirabadi, 2007, GLSVLSI '07.

Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection

Morteza Saheb Zamani, Ghobad Zarrinchian, 2017, IEEE Transactions on Computers.

An Efficient Analytical Approach to Path-Based Buffer Insertion

Morteza Saheb Zamani, Mehdi Saeedi, Hamid Reza Kheirabadi, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

An integrated temporal partitioning and physical design framework for real-time reconfigurable systems

Morteza Saheb Zamani, Kazuaki Murakami, Farhad Mehdipour, 2006 .

Parallel hardware implementation of cellular learning automata based evolutionary computing (CLA-EC) on FPGA

Mohammad Reza Meybodi, Morteza Saheb Zamani, Reza Rastegar, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

Automatic translation of quantum circuits to optimized one-way quantum computation patterns

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2014, Quantum Inf. Process..

A hierarchical layout generation method for quantum circuits

Morteza Saheb Zamani, Mehdi Sedighi, M. S. Zamani, 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability

Morteza Saheb Zamani, Ali Jahanian, Mehrdad Najibi, 2008 .

Soft IP protection: An active approach based on hardware authentication

Morteza Saheb Zamani, Mehrnoush Moradi Haghighi, 2016, 2016 24th Iranian Conference on Electrical Engineering (ICEE).

GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2006, ERSA.

Rectilinear floorplanning of FPGAs using Kohonen map

Morteza Saheb Zamani, M. Soleimani, 2003, Proceedings of the International Joint Conference on Neural Networks, 2003..

Improving hardware Trojan detection by retiming

Morteza Saheb Zamani, Seyed Mohammad Hossein Shekarian, 2015, Microprocess. Microsystems.

VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs

Morteza Saheb Zamani, Behzad Salami, Ali Jahanian, 2011, 2011 14th Euromicro Conference on Digital System Design.

Metro-on-chip: an efficient physical design technique for congestion reduction

Morteza Saheb Zamani, Ali Jahanian, M. S. Zamani, 2007, IEICE Electron. Express.

Implementation of cellular learning automata on reconfigurable computing systems

Mohammad Reza Meybodi, Morteza Saheb Zamani, Farhad Mehdipour, 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2007, ICESS.

A quantum physical design flow using ILP and graph drawing

Morteza Saheb Zamani, Mehdi Sedighi, M. S. Zamani, 2013, Quantum Inf. Process..

Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2017, ACM J. Emerg. Technol. Comput. Syst..

Improving bitstream compression by modifying FPGA architecture

Morteza Saheb Zamani, Seyyed Ahmad Razavi, 2013, FPGA '13.

GOWQS: Graph-based one-way quantum computation simulator

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2016, 2016 24th Iranian Conference on Electrical Engineering (ICEE).

An architecture framework for an adaptive extensible processor

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2008, The Journal of Supercomputing.

Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)

Morteza Saheb Zamani, Fatemeh Sadat Pourhashemi, 2012, FPGA '12.

Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology

Morteza Saheb Zamani, Ali Jahanian, Hamid Safizadeh, 2011, Integr..

Design space exploration for a coarse grain accelerator

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2008, 2008 Asia and South Pacific Design Automation Conference.

Improving Latency of Quantum Circuits by Gate Exchanging

Morteza Saheb Zamani, Mehdi Sedighi, Naser MohammadZadeh, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits

Morteza Saheb Zamani, Mehdi Sedighi, Ehsan K. Ardestani, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Specification-driven frameworks for the floorplanning and placement of hierarchical vlsi designs

Morteza Saheb Zamani, 1996 .

An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques

Morteza Saheb Zamani, Ali Jahanian, Esmaeil Khorram, 2010 .

GATE LOCATION CHANGING: AN OPTIMIZATION TECHNIQUE FOR QUANTUM CIRCUITS

Morteza Saheb Zamani, Mehdi Sedighi, M. S. Zamani, 2012 .

Evaluation, prediction and reduction of routing congestion

Morteza Saheb Zamani, Ali Jahanian, Mehdi Saeedi, 2007, Microelectron. J..

Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2007, IEICE Trans. Inf. Syst..

Reducing power consumption in FPGA routing

Morteza Saheb Zamani, E. Esmaili, M. S. Zamani, 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

Quantum circuit physical design methodology with emphasis on physical synthesis

Morteza Saheb Zamani, Mehdi Sedighi, Naser MohammadZadeh, 2014, Quantum Inf. Process..

A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems

Morteza Saheb Zamani, Hamid Fadishei, Mehdi Saeedi, 2008, Microprocess. Microsystems.

A graph-based approach to analyze flux-balanced pathways in metabolic networks

Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh, 2018, Biosyst..

Quantum physical synthesis: Improving physical design by netlist modifications

Morteza Saheb Zamani, Mehdi Sedighi, Naser MohammadZadeh, 2010, Microelectron. J..

Combinational Counters: A Low Overhead Approach to Address DPA Attacks

Morteza Saheb Zamani, Ghobad Zarrinchian, 2020, J. Circuits Syst. Comput..

Performance Improvement of Physical Retiming with Shortcut Insertion

Morteza Saheb Zamani, Ali Jahanian, Adel Dokhanchi, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement

Morteza Saheb Zamani, Minoo Mirsaeedi, Mehdi Saeedi, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme

Morteza Saheb Zamani, Arash Mehdizadeh, Hosein Shafiei, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

A neural network approach to the placement problem

Morteza Saheb Zamani, Graham R. Hellestrand, 1995, ASP-DAC '95.

A tileable switch module architecture for homogeneous 3D FPGAs

Kia Bazargan, Morteza Saheb Zamani, M. S. Zamani, 2009, 2009 IEEE International Conference on 3D System Integration.

An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor

Hossein Pedram, Morteza Saheb Zamani, Farhad Mehdipour, 2007, VLSI-SoC.

Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes

Morteza Saheb Zamani, Hamid R. Zarandi, Hassan Ebrahimi, 2011, Microelectron. J..

A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs

Morteza Saheb Zamani, Graham R. Hellestrand, 1995, IWANN.

Multi-level buffer block planning and buffer insertion for large design circuits

Morteza Saheb Zamani, Ali Jahanian, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics

Morteza Saheb Zamani, Mehdi Sedighi, Naser MohammadZadeh, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Evaluation of FPGA routing architectures under process variation

Morteza Saheb Zamani, Fatemeh Sadat Pourhashemi, 2011, GLSVLSI '11.

Synthesis of reversible circuits using a moving forward strategy

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2008, IEICE Electron. Express.

A novel synthesis algorithm for reversible circuits

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2006, Asia-Pacific Computer Systems Architecture Conference.

An efficient method for placement of VLSI designs with Kohonen map

Morteza Saheb Zamani, Farhad Mehdipour, 1999, IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339).

Prediction model for estimating leakage power consumption of routing resources in FPGAs

Morteza Saheb Zamani, Behzad Salami, 2011, 2011 3rd Asia Symposium on Quality Electronic Design (ASQED).

Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits

Morteza Saheb Zamani, Arash Mehdizadeh, 2008, 2008 IEEE/ACS International Conference on Computer Systems and Applications.

Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions

Yasaman Sanaee, Morteza Saheb Zamani, Mehdi Saeedi, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2006, EUC.

Cellular learning automata based evolutionary computing (CLA-EC) for intrinsic hardware evolution

Mohammad Reza Meybodi, Morteza Saheb Zamani, Keivan Navi, 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

A novel reconfigurable hardware architecture for IP address lookup

Masoud Sabaei, Morteza Saheb Zamani, Hamid Fadishei, 2005, 2005 Symposium on Architectures for Networking and Communications Systems (ANCS).

A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor

Morteza Saheb Zamani, Hamid Noori, Kazuaki Murakami, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Depth-optimized reversible circuit synthesis

Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh, 2012, Quantum Inf. Process..

Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates

Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh, 2014, ACM J. Emerg. Technol. Comput. Syst..

Extracting one-way quantum computation patterns from quantum circuits

Morteza Saheb Zamani, Mehdi Sedighi, Mohammad Hossein Samavatian, 2012, The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012).

A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting

Morteza Saheb Zamani, Seyed Mohammad Hossein Shekarian, Arash Nejat, 2014, Microprocess. Microsystems.

A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust

Morteza Saheb Zamani, Seyed Mohammad Hossein Shekarian, 2015, J. Circuits Syst. Comput..

A novel synthesis algorithm for reversible circuits

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2007, ICCAD 2007.

Improved timing closure by early buffer planning in floor-placement design flow

Morteza Saheb Zamani, Ali Jahanian, 2007, GLSVLSI '07.

Reducing Reconfiguration Time in FPGAs

Morteza Saheb Zamani, M. S. Zamani, S. A. Razavi, 2019, 2019 27th Iranian Conference on Electrical Engineering (ICEE).

Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2008, 2008 Asia and South Pacific Design Automation Conference.

Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2007 .

On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement

Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

An incremental temporal partitioning method for real-time reconfigurable systems

Morteza Saheb Zamani, Kazuaki Murakami, Farhad Mehdipour, 2006 .

Real-Time Activity Recognition and Intention Recognition Using a Vision-based Embedded System pdf

Morteza Saheb Zamani, Saeed Shiry Ghidary, M. S. Zamani, 2021, ArXiv.

Automated window-based partitioning of quantum circuits

Morteza Saheb Zamani, Mehdi Sedighi, Naser Mohammadzadeh, 2021 .

Geometry-based signal shifting of one-way quantum computation measurement patterns

Morteza Saheb Zamani, Mehdi Sedighi, Mahboobeh Houshmand, 2016, 2016 24th Iranian Conference on Electrical Engineering (ICEE).