M. Bhattacharya

Software reliability system modelling: a review

M. Bhattacharya, P. K. Mahanti, 2000 .

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices

Pinaki Mazumder, M. Bhattacharya, A. F. Gonzalez, 2001 .

A 250-MHz, 32-bit quantum MOS correlator prototype

Pinaki Mazumder, M. Bhattacharya, S. Kulkarni, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

Simulation and emulation of digital integrated circuits containing resonant tunneling diodes

Pinaki Mazumder, M. Bhattacharya, 1999 .

Mask-prabgrammable multiple-valued logic gate using resonant tunnellin

M. Bhattacharya, P. Mazumder, 1996 .

Noise margins of threshold logic gates containing resonant tunneling diodes

M. Bhattacharya, P. Mazumder, 2000 .

Digital circuit applications of resonant tunneling devices

Pinaki Mazumder, M. Bhattacharya, George I. Haddad, 1998, Proc. IEEE.

Mask-programmable multiple-valued logic gate using resonant tunnelling diodes

M. Bhattacharya, P. Mazumder, H.L.E. Chan, 1996 .

Monolithically integrated InP-based minority logic gate using an RTD/HBT heterostructure

Pinaki Mazumder, M. Bhattacharya, Jack R. East, 1998, Conference Proceedings. 1998 International Conference on Indium Phosphide and Related Materials (Cat. No.98CH36129).