Sumit R. Vaidya

Design of BCH Decoder Based On Multi-bit Error Correction Codes Using VHDL

Anand N . Pachare, Sumit R. Vaidya, Sandip B . Pawar, 2016 .

Performance comparison of multipliers for power-speed trade-off in VLSI design

Sumit R. Vaidya, Deepak R. Dandekar, D. Dandekar, 2010, ICN 2010.

DELAY-POWER PERFORMANCE COMPARISON OF MULTIPLIERS IN VLSI CIRCUIT DESIGN

Sumit R. Vaidya, Deepak R. Dandekar, D. Dandekar, 2010 .

A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematics

Sumit R. Vaidya, Deepak R. Dandekar, 2011, ICCCS '11.