Y. Laplanche

2007IEEEInternational SOIConference Proceedings Circuit Performance Optimization inAdvancedPD-SOICMOS Development

C. T. Tsai, J. L. Pelloie, Y. S. Huang, 2007 .

Low cost 65nm CMOS platform for Low Power & General Purpose applications

M. Woo, N. Planes, R. Palla, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Optimal PD-SOI Technology for High Performance Applications

Y.T. Huang, P.W. Liu, W.T. Chiang, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Analyze of temporal and random variability of a 45nm SOI SRAM cell

Y. Laplanche, 2009, 2009 IEEE International SOI Conference.

65nm LP/GP mix low cost platform for multi-media wireless and consumer applications

P. Abramowitz, M. Woo, N. Planes, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

J. Farkas, N. Planes, N. Revil, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

65 nm device manufacture using shaped E-Beam lithography

F. Leverd, R. Palla, M. Broekaart, 2003, Digest of Papers Microprocesses and Nanotechnology 2003. 2003 International Microprocesses and Nanotechnology Conference.

Gate stack optimization for 65 nm CMOS low power and high performance platform

R. Palla, B. Tavel, C. Ortolland, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..