Keunwoo Kim

发表

Extremely-scaled double-gate CMOS with non-self-aligned back gate

Ching-Te Chuang, Keunwoo Kim, H.I. Hanafi, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering

Ching-Te Chuang, Li-Wen Chang, Keunwoo Kim, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Assessment of structure variation in silicon nanowire FETs and impact on SRAM

Keunwoo Kim, Yi-Bo Liao, Meng-Hsueh Chiang, 2012, Microelectron. J..

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies

Ching-Te Chuang, Saibal Mukhopadhyay, Keunwoo Kim, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Impact of FinFET technology for power gating in nano-scale design

Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, 2014, Fifteenth International Symposium on Quality Electronic Design.

Process/physics-based threshold voltage model for nano-scaled double-gate devices

Ching-Te Chuang, Keunwoo Kim, Jerry G. Fossum, 2004 .

Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure

Kaushik Roy, Keith A. Jenkins, Ching-Te Chuang, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Double-Gate FET Technology for RF Applications: Device Characteristics and Low Noise Amplifier Design

Ching-Te Chuang, Keunwoo Kim, J.-O. Plouchart, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Modeling and Analysis of Leakage Currents in Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2006, 2006 European Solid-State Device Research Conference.

Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Keunwoo Kim, Jerry G. Fossum, J. Fossum, 2001 .

Novel high-density low-power high-performance double-gate logic techniques

C. Tretz, Ching-Te Chuang, Keunwoo Kim, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies

Rajiv V. Joshi, Rouwaida Kanj, Ching-Te Chuang, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Asymmetrical SRAM Cells with Enhanced Read and Write Margins

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Back-Gate Controlled Wide Tunable Range Diode Voltage in Asymmetrical Double-Gate Devices

Ching-Te Chuang, Keunwoo Kim, J.B. Kuang, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Compact Modeling Methodology of Strained-Si Channel-on-Insulator (SSOI) MOSFETs

Ching-Te Chuang, Keunwoo Kim, Jin Cai, 2004 .

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Strained-si devices and circuits for low-power applications

Rajiv V. Joshi, Ching-Te Chuang, Keunwoo Kim, 2003, ISLPED '03.

Novel High-Density Data-Retention Power Gating Structure Using a Four-Terminal Double-Gate Device

Ching-Te Chuang, Keunwoo Kim, K.K. Das, 2006, 2006 International Symposium on VLSI Design, Automation and Test.

Nanoscale CMOS circuit leakage power reduction by double-gate device

Rajiv V. Joshi, Ching-Te Chuang, Keunwoo Kim, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

FinFET SRAM Design

Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, 2010, 2010 23rd International Conference on VLSI Design.

Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2005, Sixth international symposium on quality electronic design (isqed'05).

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

Ching-Te Chuang, H.-S. Philip Wong, Keunwoo Kim, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

High-density data-retention power gating structure using a four-terminal double-gate device

Ching-Te Chuang, Keunwoo Kim, Koushik K. Das, 2007 .

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2007, Microelectron. J..

High-performance SRAM in nanoscale CMOS: Design challenges and techniques

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2007, 2007 IEEE International Workshop on Memory Technology, Design and Testing.

An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process

Ching-Te Chuang, S. Mukhopadhyay, K.A. Jenkins, 2008, IEEE Journal of Solid-State Circuits.

Development of Contact Pressure Analysis Model of Automobile Wiper Blades

Jae-Cheon Lee, Keunwoo Kim, Kyungnam Kim, 2015 .

Yield estimation of SRAM circuits using “Virtual SRAM Fab”

Rouwaida Kanj, Fook-Luen Heng, Jin-Fuw Lee, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Achieving the ballistic-limit current in Si MOSFETs

Keunwoo Kim, Jerry G. Fossum, 2003 .

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

Rajiv V. Joshi, Ching-Te Chuang, Edward J. Nowak, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

The Moderating Role of Country of Origin on the Sensitivity to Expiration date in the Sales of Online Time Commerce

Keunwoo Kim, Min Sung Kim, Jae Young Lee, 2019 .

Design and Analysis of a 10 Gbps USB 3.2 Gen 2 Type-C Connector for TV Set-Top Box

Joungho Kim, Daehwan Lho, Gapyeol Park, 2019, 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).

Variability Analysis for sub-100nm PD/SOI Sense-Amplifier

Rajiv V. Joshi, Ching-Te Chuang, Saibal Mukhopadhyay, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

A Floating-Body Dynamic Supply Boosting Technique for Low-Voltage PD/SOI CMOS SRAM

Rajiv V. Joshi, Rouwaida Kanj, Ching-Te Chuang, 2007 .

Optimal double-gate MOSFETs: symmetrical or asymmetrical gates?

Keunwoo Kim, Jerry G. Fossum, J. Fossum, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

Ching-Te Chuang, Keunwoo Kim, J.B. Kuang, 2007, IEEE Transactions on Electron Devices.

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction

Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design considerations of scaled sub-0.1 /spl mu/m PD/SOI CMOS circuits

Rajiv V. Joshi, Ching-Te Chuang, Keunwoo Kim, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

Ching-Te Chuang, Keunwoo Kim, Jie Deng, 2007, IEEE Transactions on Electron Devices.

Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2008, IEEE Transactions on Electron Devices.

Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

Ching-Te Chuang, Li-Wen Chang, Keunwoo Kim, 2009, IEEE Transactions on Electron Devices.

Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications

Ching-Te Chuang, Keunwoo Kim, Meng-Hsueh Chiang, 2008, IEEE Transactions on Electron Devices.

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

Kevin J. Nowka, Ching-Te Chuang, Fadi H. Gebara, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Back-gate controlled READ SRAM with improved stability

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2005, 2005 IEEE International SOI Conference Proceedings.

Variability Analysis for sub-100nm PD/SOI Sense-Amplifier

Ching-Te Chuang, Saibal Mukhopadhyay, Keunwoo Kim, 2008, ISQED 2008.

Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield

Rajiv V. Joshi, Rouwaida Kanj, Sani R. Nassif, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability

Ching-Te Chuang, Keunwoo Kim, Jae-Joon Kim, 2006 .

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

Rahul M. Rao, Jae-Joon Kim, Keunwoo Kim, 2010, IEEE Custom Integrated Circuits Conference 2010.

High-Performance Device Optimization and Dual-VT Technology Options for DoubleGate FET

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

Two Essays on Large-Scale Data Applications in Marketing

Keunwoo Kim, 2018 .

TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

Ching-Te Chuang, Keunwoo Kim, J.B. Kuang, 2009, IEEE Transactions on Electron Devices.

Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS

Rajiv V. Joshi, Ching-Te Chuang, Keunwoo Kim, 2004 .