Carles Hernández

发表

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

Federico Silla, Alessandro Strano, Davide Bertozzi, 2011, Int. J. Embed. Real Time Commun. Syst..

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Mario Lodde, Jose Flich, Carles Hernández, 2015, Comput. Electr. Eng..

High-Integrity GPU Designs for Critical Real-Time Automotive Systems

Jaume Abella, Sergi Alcaide, Leonidas Kosmidis, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Towards limiting the impact of timing anomalies in complex real-time processors

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2019, ASP-DAC.

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification

Jaume Abella, David de Andrés, Carles Hernández, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2018, 2018 IEEE Real-Time Systems Symposium (RTSS).

Cache Side-Channel Attacks and Time-Predictability in High-Performance Critical Real-Time Systems

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Resilient random modulo cache memories for probabilistically-analyzable real-time systems

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Improving the Performance of GALS-Based NoCs in the Presence of Process Variation

Federico Silla, José Duato, Jose Flich, 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

Francisco J. Cazorla, Jaume Abella, Sergi Alcaide, 2018, IEEE Micro.

Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study

Francisco J. Cazorla, Alen Bardizbanyan, Jaume Abella, 2017, ECRTS.

Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems

Jaume Abella, Carles Hernández, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Locality-aware cache random replacement policies

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2019, J. Syst. Archit..

Addressing Link Degradation in NoC-Based ULSI Designs

Federico Silla, José Duato, Carles Hernández, 2012, Euro-Par Workshops.

Workshop on High-performance Computing Platforms for Dependable Autonomous Systems

Mikel Azkarate-askasua, Roman Obermaisser, Jaume Abella, 2020, DSN Workshops.

LiVe: Timely error detection in light-lockstep safety critical systems

Jaume Abella, Carles Hernández, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore

Francisco J. Cazorla, Sascha Uhrig, Pascal Sainrat, 2016, TECS.

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

Enabling High-Performance Crossbars through a Floorplan-Aware Design

Federico Silla, José Duato, Jose Flich, 2012, 2012 41st International Conference on Parallel Processing.

The RECIPE approach to challenges in deeply heterogeneous high performance systems

Alessandro Cilardo, Giovanni Agosta, David Atienza, 2020, Microprocess. Microsystems.

Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

Silicon-aware distributed switch architecture for on-chip networks

Federico Silla, José Duato, Jose Flich, 2013, J. Syst. Archit..

Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Characterizing the impact of process variation on 45 nm NoC-based CMPs

Federico Silla, José Duato, Jose Flich, 2011, J. Parallel Distributed Comput..

LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A new mechanism to deal with process variability in NoC links

Federico Silla, José Duato, Carles Hernández, 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip

José Duato, Jose Flich, Tomás Picornell, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Characterizing fault propagation in safety-critical processor designs

Jaume Abella, Jaime Espinosa, Carles Hernández, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems

Francisco J. Cazorla, Jaume Abella, Eduardo Quiñones, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Low-cost checkpointing in automotive safety-relevant systems

Jaume Abella, Carles Hernández, J. Abella, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

RPR: a random replacement policy with limited pathological replacements

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2018, SAC.

Fault-Tolerant Vertical Link Design for Effective 3D Stacking

Federico Silla, José Duato, Jose Flich, 2011, IEEE Computer Architecture Letters.

Enabling TDMA Arbitration in the Context of MBPTA

Francisco J. Cazorla, Jaume Abella, Eduardo Quiñones, 2015, 2015 Euromicro Conference on Digital System Design.

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems

Alessandro Cilardo, Giovanni Agosta, David Atienza, 2018, SAMOS.

Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations

Federico Silla, José Duato, Carles Hernández, 2011, 2011 International Conference on Parallel Processing.

Adapting TDMA arbitration for measurement-based probabilistic timing analysis

Francisco J. Cazorla, Jaume Abella, Eduardo Quiñones, 2017, Microprocess. Microsystems.

An Academic RISC-V Silicon Implementation Based on Open-Source Components

Francisco J. Cazorla, Mateo Valero, Antonio Rubio, 2020, 2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS).

Distributed Training on a Highly Heterogeneous HPC System

Eduardo Quiñones, Roberto Paredes, Jose Flich, 2020, SAMOS.

HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2018, ECRTS.

A Distributed Switch Architecture for On-Chip Networks

Federico Silla, José Duato, Jose Flich, 2011, 2011 International Conference on Parallel Processing.

Fitting processor architectures for measurement-based probabilistic timing analysis

Tullio Vardanega, Francisco J. Cazorla, Jaume Abella, 2016, Microprocess. Microsystems.

Software-Only Triple Diverse Redundancy on GPUs for Autonomous Driving Platforms

Jaume Abella, Leonidas Kosmidis, Carles Hernández, 2020, 2020 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks-Supplemental Volume (DSN-S).

IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis

Irune Agirre, Mikel Azkarate-askasua, Tullio Vardanega, 2015, 2015 Euromicro Conference on Digital System Design.

Challenges in Deeply Heterogeneous High Performance Systems

Alessandro Cilardo, Giovanni Agosta, Marina Zapater, 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems

Francisco J. Cazorla, Jaume Abella, Eduardo Quiñones, 2016, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

Parallel many-core avionics systems

Francisco J. Cazorla, Jaume Abella, Eduardo Quiñones, 2014, 2014 International Conference on Embedded Software (EMSOFT).

Design and implementation of a fair credit-based bandwidth sharing scheme for buses

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Random Modulo: A new processor cache design for real-time critical systems

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A methodology for the characterization of process variation in NoC links

Federico Silla, José Duato, Carles Hernández, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Probabilistic Worst-Case Timing Analysis

Tullio Vardanega, Francisco J. Cazorla, Jaume Abella, 2019, ACM Comput. Surv..

Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2017, 2017 Euromicro Conference on Digital System Design (DSD).

Probabilistic timing analysis on time-randomized platforms for the space domain

Francisco J. Cazorla, Alen Bardizbanyan, Jaume Abella, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2017, 2017 IEEE Real-Time Systems Symposium (RTSS).

Time-Randomized Wormhole NoCs for Critical Applications

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2019, ACM J. Emerg. Technol. Comput. Syst..

Modelling bus contention during system early design stages

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2017, 2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES).

Improving performance guarantees in wormhole mesh NoC designs

Francisco J. Cazorla, Jaume Abella, Eduardo Quiñones, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Design and integration of hierarchical-placement multi-level caches for real-time systems

Francisco J. Cazorla, Jaume Abella, Carles Hernández, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores

Francisco J. Cazorla, Jaume Abella, Eduardo Quiñones, 2015, 2015 Euromicro Conference on Digital System Design.

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding

Francisco J. Cazorla, Jaume Abella, Leonidas Kosmidis, 2017, Ada-Europe.

On the Impact of Within-Die Process Variation in GALS-Based NoC Performance

Federico Silla, José Duato, Jose Flich, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

DIMP: A low-cost diversity metric based on circuit path analysis

Jaume Abella, Sergi Alcaide, Carles Hernández, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

WCET analysis methods: Pitfalls and challenges on their trustworthiness

Mikel Azkarate-askasua, Tullio Vardanega, Francisco J. Cazorla, 2015, 10th IEEE International Symposium on Industrial Embedded Systems (SIES).

PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis

Liliana Cucu-Grosjean, Irune Agirre, Mikel Azkarate-askasua, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem

Oriol Farràs, Jordi Ribes-González, Carles Hernández, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience

Jose Flich, Carles Hernández, Rafael Tornero, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).