J. Liu

SMT and enhanced SPT with recessed SD to improve CMOS device performance

E. Maciejewski, E. Leobandung, J.J. Kim, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

K. McStay, G. Freeman, R. Krishnan, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

T. Kirihata, A. Blauberg, S. Narasimha, 2010, 2010 International Electron Devices Meeting.

32nm general purpose bulk CMOS technology for high performance applications at low voltage

S. Samavedam, M. Sherony, F. Arnaud, 2008, 2008 IEEE International Electron Devices Meeting.

A 0.13 /spl mu/m logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 /spl mu/m generation

B.J. Park, D. Shum, J. Liu, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 0.168/spl mu/m/sup 2//0.11/spl mu/m/sup 2/ highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

T. Kirihata, S.S. Iyer, J. Liu, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation

J. Safran, J. Liu, J. Golz, 2014, 2014 IEEE International Electron Devices Meeting.