Kobatake Hiroyuki

发表

Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs

Nomura Masahiro, Hayashi Yoshihiro, Takeuchi Kiyoshi, 2011 .

Redefinition of Write Margin for Next-Generation SRAMs and Write-Margin Monitoring Circuits

Nomura Masahiro, Takeda Koichi, Kobatake Hiroyuki, 2006 .

A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications

Nomura Masahiro, Takeda Koichi, Aimoto Yoshiharu, 2005 .