Siyoung Choi

Qualification method for DRAM retention by leakage current evaluation using subthreshold characteristics of cell transistors

Young Pil Kim, Beom Jun Jin, Sun-Ghil Lee, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

High performance cell technology featuring sub-100nm DRAM with multi-gigabit density

Joo-Tae Moon, U-In Chung, Cheol-Sung Kim, 2002, Digest. International Electron Devices Meeting,.

5G K-SimNet: End-to-End Performance Evaluation of 5G Cellular Systems

Ted Taekyoung Kwon, Saewoong Bahk, Sunghyun Choi, 2019, 2019 16th IEEE Annual Consumer Communications & Networking Conference (CCNC).

Aggressively scaled high-k last metal gate stack with low variability for 20nm logic high performance and low power applications

Chilhee Chung, H.-S. Hong, Siyoung Choi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)

Siyoung Choi, K.L. Wang, Sung Min Kim, 2006, 2009 Symposium on VLSI Technology.

Short-interval expository real-time scheduling of semiconductor manufacturing with mixed integer programming

Siyoung Choi, Myoungsoo Ham, 2014, Proceedings of the Winter Simulation Conference 2014.

Future logic device technologies beyond the 28nm node

Chilhee Chung, Siyoung Choi, Jong Shik Yoon, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

An array cell transistor test structure for the leakage current analysis of stacked capacitor DRAMs with diagonal cell scheme

Gi-Sung Yeo, Young Pil Kim, Beom Jun Jin, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

Optimal Beamforming and Power Allocation for Sensing-Based Spectrum Sharing in Cognitive Radio Networks

Taewon Hwang, Hyunsung Park, Siyoung Choi, 2014, IEEE Transactions on Vehicular Technology.