A. De Keersgieter

发表

Unexpected failure during HBM ESD stress in nanometer-scale nLDMOS-SCR devices

G. Groeseneken, D. Linten, S. Thijs, 2011, 2011 International Electron Devices Meeting.

Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations

P. Eyben, D. Mocuta, J. Mitard, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Location and hardness of the oxide breakdown in short channel n- and p-MOSFETs

R. Degraeve, B. Kaczer, F. Crupi, 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages

J. G. Fossum, N. Collaert, M. Jurczak, 2010, 2010 International Electron Devices Meeting.

Relation between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications

R. Degraeve, B. Kaczer, A. De Keersgieter, 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

B. Parvais, R. Rooyackers, A. Mercha, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Multi-gate devices for the 32nm technology node and beyond

R. Rooyackers, A. Mercha, L. Witters, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

B. Parvais, A. Brand, N. Horiguchi, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

E. Simoen, G. Hellings, E. Vecchio, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

R. Rooyackers, T. Skotnicki, N. Collaert, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology

L. Breuil, P. Blomme, J. Van Houdt, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

R. Rooyackers, N. Collaert, G. Eneman, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Quantum-barriers and ground-plane isolation: A path for scaling bulk-FinFET technologies to the 7 nm-node and beyond

G. Hellings, N. Collaert, G. Eneman, 2013, 2013 IEEE International Electron Devices Meeting.

Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

L. Deferm, P. Jansen, D. Kerr, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Schottky-Barrier Height Lowering by an Increase of the Substrate Doping in PtSi Schottky Barrier Source/Drain FETs

E. Augendre, S. Biesemans, M. Jurczak, 2007, IEEE Electron Device Letters.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

R. Rooyackers, N. Collaert, S. Biesemans, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Scalability of strained nitride capping layers for future CMOS generations

G. Eneman, M. Jurczak, K. De Meyer, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Channel Hot-Carrier degradation under static stress in short channel transistors with high-k/metal gate stacks

R. Degraeve, M. Nafria, G. Groeseneken, 2008, 2008 9th International Conference on Ultimate Integration of Silicon.

Integration challenges for multi-gate devices

R. Rooyackers, S. De Gendt, S. Locorotondo, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

N. Collaert, J. Mitard, M. Jurczak, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study

G. Eneman, M. Jurczak, K. De Meyer, 2007, IEEE Transactions on Electron Devices.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Optimization of Sub-Melt Laser Anneal: Performance and Reliability

S. Mahapatra, S. Severi, L. Pantisano, 2006, 2006 International Electron Devices Meeting.

New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs

B. Kaczer, F. Crupi, G. Groeseneken, 2003, IEEE Electron Device Letters.

Understanding nMOSFET Characteristics after Soft Breakdown and Their Dependence on the Breakdown Location

R. Degraeve, B. Kaczer, F. Crupi, 2002, 32nd European Solid-State Device Research Conference.