S. Saxena

Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability

S. Saxena, S. Minehane, J. Cheng, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

Optimal distributed leader election algorithm for synchronous complete network

S. Saxena, P. Francis, 1998, Proceedings of IEEE TENCON '98. IEEE Region 10 International Conference on Global Connectivity in Energy, Computer, Communication and Control (Cat. No.98CH36229).