Meishoku Masahara

发表

Ultra-Compact Si-Wire 8 8 Strictly-Non-Blocking PILOSS Switch

Yasushi Igarashi, Ken Tanizawa, Keijiro Suzuki, 2013 .

Vertical double-gate MOSFET device technology

Meishoku Masahara, Yongxun Liu, Kazuhiko Endo, 2008 .

Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO2 gate stacks

Meishoku Masahara, Shinji Migita, Yukinori Morita, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

Meishoku Masahara, Kazuhiko Endo, Takashi Matsukawa, 2008 .

Highly Reliable SRAM Circuit Technology Using FinFETs

Hiromi Yamauchi, Meishoku Masahara, Kazuhiko Endo, 2009 .

Enhancing SRAM performance by advanced FinFET device and circuit technology collaboration for 14nm node and beyond

Meishoku Masahara, Shinji Migita, Kazuhiko Endo, 2013, 2013 Symposium on VLSI Circuits.

Vertical Double-Gate MOSFET Device Technology

Meishoku Masahara, Yongxun Liu, Kazuhiko Endo, 2006 .

Vertical ultrathin‐channel multi‐gate MOSFETs (MuGFETs): technological challenges and future developments

Meishoku Masahara, Yongxun Liu, Kazuhiko Endo, 2009 .

Variability Analysis of TiN FinFET SRAM Cells and Its Compensation by Independent-DG FinFETs

Hiromi Yamauchi, Kunihiro Sakamoto, Takashi Matsukawa, 2010, IEEE Electron Device Letters.

Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET

Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, 2010, IEEE Custom Integrated Circuits Conference 2010.

(Invited) On-Current Variability Sources of FinFETs: Analysis and Perspective for 14nm-Lg Technology

Meishoku Masahara, Shin-ichi O'uchi, Yongxun Liu, 2012 .

Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

In Man Kang, James S. Harris, Sang Wan Kim, 2010 .

0.8-V rail-to-rail operational amplifier with near-Vt gain-boosting stage fabricated in FinFET technology for IoT sensor nodes

Takashi Matsukawa, Meishoku Masahara, Tadashi Nakagawa, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

May the fourth (terminal) be with you - circuit design beyond FinFET

Kunihiro Sakamoto, Toshiyuki Tsutsumi, Takashi Matsukawa, 2010, 2010 International Electron Devices Meeting.

Variability origins of FinFETs and perspective beyond 20nm node

Takashi Matsukawa, Meishoku Masahara, Shin-ichi O'uchi, 2011, IEEE 2011 International SOI Conference.

Double-gate FINFET innovation: From 3-terminal to flexible threshold voltage 4-terminal

Meishoku Masahara, Yongxun Liu, Kenlchi Ishii, 2004 .

Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology

Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, 2008 .

Invited) FinFET Flash Memory Technology

Hiromi Yamauchi, Meishoku Masahara, Atsushi Ogura, 2012 .

Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration

Takashi Matsukawa, Meishoku Masahara, K. Fukuda, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Correlative analysis between characteristics of 30-nm LG FinFETs and SRAM performance

Hiromi Yamauchi, Kunihiro Sakamoto, Takashi Matsukawa, 2011, 2011 International Electron Devices Meeting.

INVITED PAPER Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology Independent-Double-Gate FinFET SRAM Technology

Nonmembers, Meishoku Masahara, Yongxun Liu, 2013 .

(Invited) Independent-Double-Gate FinFET SRAM Technology

Meishoku Masahara, Shin-ichi O'uchi, Kazuhiko Endo, 2013 .

Emerging double-gate MOS devices technology

Kenichi Ishii, Meishoku Masahara, Eiichi Suzuki, 2003 .

SOI CMOS Voltage Multiplier Circuits with Body Bias Control Technique for Battery-Less Wireless Sensor System

Yasushi Igarashi, Kunihiro Sakamoto, Meishoku Masahara, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Fabrication and Power-Management Demonstration of Four-Terminal FinFETs

Meishoku Masahara, Shin-ichi O'uchi, Kazuhiko Endo, 2007 .

High-Frequency Precise Characterization of Intrinsic FinFET Channel

Hiroki Ishikuro, Kunihiro Sakamoto, Hanpei Koike, 2012, IEICE Trans. Electron..

Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology

Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Robust and compact key generator using physically unclonable function based on logic-transistor-compatible poly-crystalline-Si channel FinFET technology

Yohei Hori, Hiroshi Fuketa, Takashi Matsukawa, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction

Kunihiro Sakamoto, Hanpei Koike, Takashi Matsukawa, 2008, IEICE Trans. Electron..

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo, 2014 .

Static noise margin enhancement by flex-pass-gate SRAM

Meishoku Masahara, Shin-ichi O'uchi, Kazuhiko Endo, 2011 .

PBTI for N-type tunnel FinFETs

Hiromi Yamauchi, Yuki Ishikawa, Takashi Matsukawa, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Independent double-gate FinFET SRAM technology

Takashi Matsukawa, Meishoku Masahara, Yongxun Liu, 2011, The 4th IEEE International NanoElectronics Conference.

Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations

Takashi Matsukawa, Meishoku Masahara, K. Fukuda, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes

Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology

Hiromi Yamauchi, Kunihiro Sakamoto, Hanpei Koike, 2012, IEICE Trans. Electron..

Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance

Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Low Temperature, Beam-Orientation-Dependent, Lattice-Plane-Independent, and Damage-Free Oxidation for Three-Dimensional Structure by Neutral Beam Oxidation

Takashi Matsukawa, Meishoku Masahara, Seiji Samukawa, 2009 .

Unexpected equivalent-oxide-thickness dependence of the subthreshold swing in tunnel field-effect transistors

Meishoku Masahara, Tetsuji Yasuda, A. Tanabe, 2014 .

Impact of thermal history of Si nanowire fabrication process on Ni silicidation rate

Jing Sun, Takashi Matsukawa, Meishoku Masahara, 2014 .

Variability Analysis of TiN Metal-Gate FinFETs

Hiromi Yamauchi, Kunihiro Sakamoto, Takashi Matsukawa, 2010, IEEE Electron Device Letters.

Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI

Takashi Matsukawa, Meishoku Masahara, Shinji Migita, 2014, IEEE Transactions on Nanotechnology.

On the nonlocal modeling of tunnel-FETs Device and Compact models

Meishoku Masahara, Tetsuji Yasuda, Shinji Migita, 2013 .

Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect

Takashi Matsukawa, Meishoku Masahara, Shinji Migita, 2014, IEEE Electron Device Letters.

Ultra-Compact 8 x 8 Strictly Non-Blocking PILOSS Switch Based on Si-Wire

Ken Tanizawa, Shu Namiki, Keijiro Suzuki, 2014 .

Tunnel Field-Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes

Meishoku Masahara, A. Tanabe, Shinji Migita, 2013 .

Demonstration and Analysis of Accumulation-Mode Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor

Kenichi Ishii, Takashi Matsukawa, Meishoku Masahara, 2006 .

Spatial variation of the work function in nano-crystalline TiN films measured by dual-mode scanning tunneling microscopy

Takashi Matsukawa, Meishoku Masahara, Koichi Fukuda, 2014 .

Fabrication of ultrathin Si Channel Wall For Vertical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG MOSFET) by Using Ion-Bombardment-Retarded Etching (IBRE)

Kenichi Ishii, Takashi Matsukawa, Meishoku Masahara, 2003 .

Comprehensive analysis of Ion variation in metal gate FinFETs for 20nm and beyond

Hiromi Yamauchi, Kunihiro Sakamoto, Takashi Matsukawa, 2011, 2011 International Electron Devices Meeting.

Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory

Hiroshi Fuketa, Takashi Matsukawa, Meishoku Masahara, 2016 .

Enhancing Noise Margins of Fin-Type Field Effect Transistor Static Random Access Memory Cell by Using Threshold Voltage-Controllable Flexible-Pass-Gates

Hiromi Yamauchi, Kunihiro Sakamoto, Kenichi Ishii, 2009 .

Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Hiromi Yamauchi, Kunihiro Sakamoto, T. Hayashida, 2012 .

Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors

Kunihiro Sakamoto, Kenichi Ishii, Takashi Matsukawa, 2005 .

Fabrication and Demonstration of 3-nm-Channel-Length Junctionless Field-Effect Transistors on Silicon-on-Insulator Substrates Using Anisotropic Wet Etching and Lateral Diffusion of Dopants (Special Issue : Solid State Devices and Materials)

Meishoku Masahara, Shinji Migita, Yukinori Morita, 2013 .

Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography

Kenichi Ishii, H. Takashima, Toshiyuki Tsutsumi, 2003 .

Tunnel Field-Effect Transistors with Extremely Low Off-Current Using Shadowing Effect in Drain Implantation

Kunihiro Sakamoto, Meishoku Masahara, Tetsuji Yasuda, 2011 .

Ultra-compact 8 × 8 strictly-non-blocking Si-wire PILOSS switch.

Ken Tanizawa, Shu Namiki, Keijiro Suzuki, 2014, Optics express.

Demonstration of Dopant Profiling in Ultrathin Channels of Vertical-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect-Transistor by Scanning Nonlinear Dielectric Microscopy

Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo, 2005 .

Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Byung-Gook Park, Seongjae Cho, Meishoku Masahara, 2009, 2009 International Semiconductor Device Research Symposium.

Independent double-gate FinFET SRAM technology

Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo, 2011 .