A. Jerraya

Global modeling and simulation of System-on-Chip embedding MEMS devices

G. Nicolescu, K. Torki, B. Courtois, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

DLS: A scheduling algorithm for high-level synthesis in VHDL

A. Jerraya, K. O'Brien, M. Rahmouni, 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.