Mao Zhi-gang

A Design of Address Generation Unit of Digital Signal Processor

Mao Zhi-gang, 2009 .

A high speed 0.25 /spl mu/m 64-bit CMOS adder design

Mao Zhi-gang, Ye Yi-zheng, Lai Feng-chang, 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

Efficient frame-level pipelined array architecture for full-search block-matching motion estimation

Mao Zhi-gang, He Wei-feng, Bi Yun-long, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Design of 6-port High-speed and Low-power Partitioned Register File

Mao Zhi-gang, 2009 .

Design of an efficient ALU based on reused logic structure

Mao Zhi-gang, 2010 .

Design and Optimization of a Barrel Shifter Unit for DSP

Mao Zhi-gang, 2009 .

Linking Words in Mr.Ma's Grammar and Some Related Questions

Mao Zhi-gang, 2009 .

Design and realization of a multifunctional LCD controller based on FPGA

Mao Zhi-gang, 2008 .

The discussion of direct reduction the new technology

Mao Zhi-gang, 2006 .

A 64 bit parallel CMOS adder for high performance processors

Mao Zhi-gang, Lai Feng-chang, Sun Xu-guang, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Implementation of half-pel motion estimation IP core for MPEG-4 ASP@L5 texture coding

Zhang Yan, Mao Zhi-gang, Gao Zhi-qiang, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..