Abusaleh M. Jabir

发表

IEEE High-Level Design Validation and Test Workshop

Dhiraj K. Pradhan, Hafizur Rahaman, J Matthew, 2006 .

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Single error correctable bit parallel multipliers over GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2009, IET Comput. Digit. Tech..

Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme

Jimson Mathew, Abusaleh M. Jabir, Adedotun Adeyemo, 2017, J. Low Power Electron..

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations

Eugenio Martinelli, Abusaleh M. Jabir, Corrado Di Natale, 2020, 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF $(2^{m})$

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Novel memristive logic architectures

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2016, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

MODD for CF: a representation for fast evaluation of multiple-output functions

Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

A Galois field-based logic synthesis with testability

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2010, IET Comput. Digit. Tech..

Fault Resilient Galois Field Multiplier Design in Emerging Technologies

Jimson Mathew, Abusaleh M. Jabir, Mahesh Poolakkaparambil, 2012 .

Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)

Jimson Mathew, Abusaleh M. Jabir, Mahesh Poolakkaparambil, 2012 .

High-performance single-cycle memristive multifunction logic architecture

Jimson Mathew, Abusaleh M. Jabir, Adedotun Adeyemo, 2016 .

A Memristive Activation Circuit for Deep Learning Neural Networks

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2018, 2018 8th International Symposium on Embedded Computing and System Design (ISED).

GASIM: a fast Galois field based simulator for functional model

Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh, 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..

Learning method for ex-situ training of memristor crossbar based multi-layer neural network

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2017, 2017 9th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT).

A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

An efficient technique for synthesis and optimization of polynomials in GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2006, ICCAD.

Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, 2010 .

BCH code based multiple bit error correction in finite field multiplier circuits

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, 2011 12th International Symposium on Quality Electronic Design.

Fault tolerant bit parallel finite field multipliers using LDPC codes

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields

Dhiraj K. Pradhan, Abusaleh M. Jabir, 2007, IEEE Transactions on Computers.

High level abstraction of memristor model for neural network simulation

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2016, 2016 Sixth International Symposium on Embedded Computing and System Design (ISED).

On the synthesis of attack tolerant cryptographic hardware

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

Write scheme for multiple Complementary Resistive Switch (CRS) cells

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Logic minimization algorithms for three-level AND-OR-EXOR representations

Abusaleh M. Jabir, 2001 .

Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2010, IET Comput. Digit. Tech..

Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2019, J. Low Power Electron..

C-testable bit parallel multipliers over GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, TODE.

Efficient sensing approaches for high-density memristor sensor array

Jimson Mathew, Marco Ottavi, Abusaleh M. Jabir, 2018 .

On the design of different concurrent EDC schemes for S-Box and GF(p)

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh, 2007, IEEE Transactions on Computers.

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2013, Comput. Electr. Eng..

Analytic models for crossbar read operation

Jimson Mathew, Abusaleh M. Jabir, Adedotun Adeyemo, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

MODD: a new decision diagram and representation for multiple output binary functions

Dhiraj K. Pradhan, Abusaleh M. Jabir, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, IEEE Transactions on Computers.

Secure memristor replicator architecture with physical uncloneability

Abusaleh M. Jabir, Saurabh Khandelwal, X. Yang, 2019, Electronics Letters.

International Symposium on Electronic System Design (ISED)

Jimson Mathew, Abusaleh M. Jabir, Pradhan Dhiraj, 2010 .

A Galois Field Based Logic Synthesis Approach with Testability

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Reliable gas sensing with memristive array

Jimson Mathew, Marco Ottavi, Abusaleh M. Jabir, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Single Error Correcting Finite Field Multipliers Over GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Reliable gas sensing with memristive crossbar array

Jimson Mathew, Marco Ottavi, Abusaleh M. Jabir, 2017 .

Novel techniques for memristive multifunction logic design

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2019, Integr..

Parasitic effects on memristive logic architecture

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2017, 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Low complexity cross parity codes for multiple and random bit error correction

Jimson Mathew, Saraju P. Mohanty, Abusaleh M. Jabir, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

C-testable S-box implementation for secure advanced encryption standard

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2009, 2009 15th IEEE International On-Line Testing Symposium.

Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2008, 2008 14th IEEE International On-Line Testing Symposium.

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2012, VDAT.

An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies

Jimson Mathew, Saraju P. Mohanty, Abusaleh M. Jabir, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Analytic models for crossbar write operation

Abusaleh M. Jabir, Adedotun Adeyemo, Xiaohan Yang, 2016, 2016 Sixth International Symposium on Embedded Computing and System Design (ISED).

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

21st Conference on VLSI Design VLSI 08

Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, 2008 .

Reliability Assessment of Memristor based Gas Sensor Array

Marco Ottavi, Abusaleh M. Jabir, Eugenio Martinelli, 2021, 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations

Marco Ottavi, Abusaleh M. Jabir, Eugenio Martinelli, 2021, 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Galois Switching Theory: A Uniform Framework for Multi-Level Verification

Dhiraj K. Pradhan, Abusaleh M. Jabir, A. D. Singh, 2005 .