Kyowon Jin

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

Ji Hwan Park, Jiho Choi, Seong Hee Lee, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

Dongkyun Kim, Minsu Park, Mingyu Park, 2020, IEEE Journal of Solid-State Circuits.

A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture

Sung-Wook Choi, Woopyo Jeong, Sunghwa Ok, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).