S. Gurunarayanan

发表

EFFS: Efficient Flash File System for Wireless Sensor Nodes

Biju K. Raveendran, Janardan Prasad Misra, Karan Bhatnagar, 2007, ESA.

Design and Analysis of a Hybrid Non-volatile SRAM Cell for Energy Autonomous IoT

Nitin Chaturvedi, Kanika, S. Gurunarayanan, 2019 .

An efficient method to compute static single assignment form for multicore architecture

Janardan Prasad Misra, S. Gurunarayanan, D. C. Kiran, 2012, 2012 1st International Conference on Recent Advances in Information Technology (RAIT).

STUDY OF VARIOUS FACTORS AFFECTING PERFORMANCE OF MULTI-CORE PROCESSORS

Nitin Chaturvedi, S. Gurunarayanan, 2013 .

A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling

Biju K. Raveendran, S. Gurunarayanan, Sundar Balasubramaniam, 2006, Asia-Pacific Computer Systems Architecture Conference.

An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets

Nirwan Ansari, Vinay Chamola, S. Gurunarayanan, 2020, Future Gener. Comput. Syst..

Design of an Efficient Low-Power AES Engine for Zigbee Systems

Sudarshan Tsb, S. Gurunarayanan, Ninad B Kothari, 2006 .

An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System

Biju K. Raveendran, T. S. B. Sudarshan, S. Gurunarayanan, 2007, ESA.

SOC design of a Low Power Wireless Sensor network node for Zigbee Systems

S. Gurunarayanan, Chandrasekhar, N.B. Kothari, 2006, 2006 International Conference on Advanced Computing and Communications.

Integrated Cooperative Synchronization for Wireless Sensor Networks

Andreas Springer, S. Gurunarayanan, Bernhard Etzlinger, 2019, IEEE Wireless Communications Letters.

Compiler Assisted Dynamic Scheduling for Multicore Processors

S. Gurunarayanan, D. C. Kiran, B. Radheshyam, 2011, 2011 International Conference on Process Automation, Control and Computing.

Modified Way Predictive Set-Associative Cache for Energy Efficient Embedded Systems

Biju K. Raveendran, S. Gurunarayanan, Tsb Sudarshan, 2008 .

Energy-efficient data retention in D flip-flops using STT-MTJ

Nitin Chaturvedi, S. Gurunarayanan, Kanika Monga, 2020 .

Adaptive Zone-Aware Multi-bank on Chip Last Level L2 Cache Partitioning for Chip Multiprocessors

Nitin Chaturvedi, S. Gurunarayanan, Jithin P. Thomas, 2010 .

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure

Chandra Shekhar, Arindam Karmakar, S. Gurunarayanan, 2015, 2015 19th International Symposium on VLSI Design and Test.

Predictive Placement Scheme In Set-Associative Cache For Energy Efficient Embedded Systems

S. Gurunarayanan, Abhinandan H. Patil, T.S.B. Sudarshan, 2008, 2008 International Conference on Signal Processing, Communications and Networking.

Integrated scheduling and register allocation for multicore architecture

S. Gurunarayanan, D. C. Kiran, J. P. Misra, 2013, 2013 National Conference on Parallel Computing Technologies (PARCOMPTECH).

E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster- Based Wireless Sensor Networks

Biplab Sikdar, Vinay Chamola, S. Gurunarayanan, 2019, IEEE Sensors Journal.

Evaluation of priority based real time scheduling algorithms: choices and tradeoffs

Biju K. Raveendran, S. Gurunarayanan, Sundar Balasubramaniam, 2008, SAC '08.

Design of an MTJ/CMOS-based Asynchronous System for Ultra-Low Power Energy Autonomous Applications

Nitin Chaturvedi, S. Gurunarayanan, Kanika Monga, 2020 .

Selective Cache Line Replication Scheme in Shared Last Level Cache

Arun Subramaniyan, Nitin Chaturvedi, S. Gurunarayanan, 2015 .

Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications

Nitin Chaturvedi, S. Gurunarayanan, Kanika Monga, 2020 .

An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-core Architectures

Nitin Chaturvedi, S. Gurunarayanan, 2013, 2013 5th International Conference on Computational Intelligence and Communication Networks.

Compiler Driven Inter Block Parallelism for Multicore Processors

S. Gurunarayanan, D. C. Kiran, J. P. Misra, 2012 .

A comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell design

Nitin Chaturvedi, S. Gurunarayanan, Divya Suneja, 2017, 2017 International Conference on Computer, Communications and Electronics (Comptelix).

Platform-Based Design Approach for Embedded Vision Applications

Abhijit Karmakar, S. Gurunarayanan, Jai Gopal Pandey, 2013 .

Selective Placement Data Cache for Low Energy Embedded System

S. Gurunarayanan, T.S.B. Sudarshan, B.K. Raveendran, 2006, 2006 International Conference on Advanced Computing and Communications.

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Nitin Chaturvedi, Kanika, S. Gurunarayanan, 2019, Integr..

An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications

A. Karmakar, S. Gurunarayanan, J. G. Pandey, 2015, 2015 28th International Conference on VLSI Design.

Implementation of an improved connected component labeling algorithm using FPGA-based platform

A. Karmakar, S. Gurunarayanan, A. K. Mishra, 2014, 2014 International Conference on Signal Processing and Communications (SPCOM).

Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems

Biju K. Raveendran, S. Gurunarayanan, Sundar Balasubramaniam, 2006, ICDCN.

Variable Partitioning to Solve Dual Bank Register Allocation for Network Processor

Sudarshan Tsb, S. Gurunarayanan, D C Kiran, 2008, HiPC 2008.

Adaptive Block Pinning Based: Dynamic Cache Partitioning for Multi-core Architectures

Nitin Chaturvedi, S. Gurunarayanan, Jithin P. Thomas, 2010 .

An efficient adaptive block pinning for multicore architectures

Nitin Chaturvedi, S. Gurunarayanan, N. Chaturvedi, 2015, Microprocess. Microsystems.

An adaptive coherence protocol with adaptive cache for multi-core architectures

Nitin Chaturvedi, S. Gurunarayanan, Pawan Sharma, 2013, 2013 International Conference on Advanced Electronic Systems (ICAES).

Global Scheduling Heuristics for Multicore Architecture

Janardan Prasad Misra, S. Gurunarayanan, D. C. Kiran, 2015, Sci. Program..

Taming Compiler to Work with Multicore Processors

S. Gurunarayanan, D. C. Kiran, J. P. Misra, 2011, 2011 International Conference on Process Automation, Control and Computing.

Design of a Robust Logic Gate using Magnetic Tunnel Junction

Nitin Chaturvedi, S. Gurunarayanan, Kanika Monga, 2019, 2019 IEEE 16th India Council International Conference (INDICON).

A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT

Vinay Chamola, S. Gurunarayanan, G. Sai Sesha Chalapathi, 2019, J. Intell. Fuzzy Syst..

Fine grain thread scheduling on multicore processors: cores with multiple functional units

Janardan Prasad Misra, S. Gurunarayanan, D. C. Kiran, 2013, COMPUTE.

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm

Chandra Shekhar, Arindam Karmakar, S. Gurunarayanan, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

S. Gurunarayanan, D. C. Kiran, Munish Bhatia, 2017, J. King Saud Univ. Comput. Inf. Sci..

An FPGA-Based Novel Architecture for the Fixed-Point Binary Antilogarithmic Computation

A. Karmakar, S. Gurunarayanan, J. G. Pandey, 2014, 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies.

Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array

Nitin Chaturvedi, S. Gurunarayanan, Kanika Monga, 2020, 2020 24th International Symposium on VLSI Design and Test (VDAT).

An adaptive migration–replication scheme (AMR) for shared cache in chip multiprocessors

Arun Subramaniyan, Nitin Chaturvedi, S. Gurunarayanan, 2015, The Journal of Supercomputing.

An FPGA-based fixed-point architecture for binary logarithmic computation

A. Karmakar, S. Gurunarayanan, J. G. Pandey, 2013, 2013 IEEE Second International Conference on Image Information Processing (ICIIP-2013).

Cache Memory Design with Late Replacements for Embedded Systems

Biju K. Raveendran, S. Gurunarayanan, Tsb Sudarshan, 2006 .

LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache

S. Gurunarayanan, T.S.B. Sudarshan, B.K. Raveendran, 2007, 15th International Conference on Advanced Computing and Communications (ADCOM 2007).

An exploration of neuromorphic systems and related design issues/challenges in dark silicon era

Nitin Chaturvedi, S. Gurunarayanan, Mudit Chandaliya, 2018 .

Architectures and algorithms for image and video processing using FPGA-based platform

Arindam Karmakar, S. Gurunarayanan, Jai Gopal Pandey, 2014, 18th International Symposium on VLSI Design and Test.

Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architecture

S. Gurunarayanan, D. C. Kiran, Faizan Khaliq, 2012 .