Jürgen Schietke

Cycle time and slack optimization for VLSI-chips

Jens Vygen, Christoph Albrecht, Bernhard Korte, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip 3

Jens Vygen, Christoph Albrecht, Bernhard Korte, 2001 .

Platzierungsbasierte Logikoptimierung komplexer VLSI Chips

Jürgen Koehl, Jürgen Schietke, 2000, MBMV.

Timing analysis and optimization of a high-performance CMOS processor chipset

Jürgen Schietke, Uwe Fassnacht, 1998, Proceedings Design, Automation and Test in Europe.