Wen Xiaoqing

发表

Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test

Tanaka Hiroaki, Kajihara Seiji, Miyase Kohei, 2012 .

Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test

Wen Xiaoqing, Holst Stefan, Shi Shiling, 2019 .

A Method to Estimate the Number of Don't-Care Bits with Netlist

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2012 .

Locating Hot Spots with Justification Techniques in a Layout Design

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2018 .

An expanded Per-Test X-Fault Diagnosis Method for LSI Circuits

Nakamura Yusuke, Kajihara Seiji, Miyase Kohei, 2007 .

Power Analysis for Logic Area of LSI Including Memory Area

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2020 .

Equivalence fault collapsing for transistor leakage faults

Wen Xiaoqing, H. Tamamoto, K.K. Saluja, 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test

Kajihara Seiji, Wen Xiaoqing, Yamato Yuta, 2016 .

On Avoiding Test Data Corruption by Optimal Scan Chain Grouping

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2017 .

Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2011 .

Efficient Methods for Guided-Probe Diagnosis (Special Issue on VLSI Testing and Testable Design)

Kozo Kinoshita, Noriyoshi Itazaki, Wen Xiaoqing, 1993 .

A Capture-Safe Test Generation Scheme for At-speed Scan Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2008 .

On Optimal Power-Aware Path Sensitization

Jiang Jie, Miyase Kohei, Wen Xiaoqing, 2016 .

Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification

Kajihara Seiji, Miyase Kohei, Enokimoto Kazunari, 2011 .

Improving Controllability of Signal Transitions in the High Switching Area of LSI

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2020 .

A new testable design of logic circuits under highly observable condition

Kozo Kinoshita, Hideo Tamamoto, Wen Xiaoqing, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Fault diagnosis for static CMOS circuits

Kozo Kinoshita, Hideo Tamamoto, Kewal K. Saluja, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2016 .

A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2007 .

Transistor Leakage Fault Diagnosis with I DDQ and Logic Information

Kozo Kinoshita, Hideo Tamamoto, Kewal K. Saluja, 1998 .

重み付き擬似ランダムテストパターン生成と追播に基づく低電力スキャンベース組込み自己テスト【Powered by NICT】

Xiang Dong, Wen Xiaoqing, Wang Laung-Terng, 2017 .

A Constrained Test Generation Method for Low Power Testing

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2007 .

Transistor Aging and Operational Environment of Logic Circuits

Sato Yasuo, Kajihara Seiji, Miyase Kohei, 2008 .

IR-Drop Analysis on Different Power Supply Network Designs

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2017 .

Improving Controllability of Switching Activity for Specified Areas in the LSI

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2020 .

A Method to Identify High Test Power Areas in Layout Design

Kajihara Seiji, Miyase Kohei, Wen Xiaoqing, 2015 .