Ganesh Lakshminarayana

发表

Common-case computation: a high-level energy and performance optimization technique

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

COSYN: hardware-software co-synthesis of embedded systems

Niraj K. Jha, Ganesh Lakshminarayana, Bharat P. Dave, 1997, DAC.

Transient power management through high level synthesis

Srivaths Ravi, Ganesh Lakshminarayana, Anand Raghunathan, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Common-case computation: a high-level technique for power and performance optimization

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1999, DAC '99.

High-level test compaction techniques

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

High-level software energy macro-modeling

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

TAO: regular expression-based register-transfer level testability analysis and optimization

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Reducing test application time in high-level test generation

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Wavesched: a novel scheduling technique for control-flow intensive designs

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors

Niraj K. Jha, Ganesh Lakshminarayana, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design of high-performance system-on-chips using communication architecture tuners

Sujit Dey, Ganesh Lakshminarayana, Anand Raghunathan, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High-level energy macromodeling of embedded software

Niraj K. Jha, Ganesh Lakshminarayana, Tat Kee Tan, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A framework for testing core-based systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Input space adaptive embedded software synthesis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Accurate power macro-modeling techniques for complex RTL circuits

Michael S. Hsiao, Ganesh Lakshminarayana, Anand Raghunathan, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Input space adaptive design: a high-level methodology for energy and performance optimization

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Wavesched: A Novel Scheduling Technique For Control-flow Behavioral Descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Kamd S. Khouri, 1997 .

TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Algorithm Exploration for Efficient Public-Key Security Processing on Wireless Handsets

Ganesh Lakshminarayana, Anand Raghunathan, Srivaths Ravi, 2002 .

: a novel scheduling technique for control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, K. S. Khouri, 1997, ICCAD 1997.

FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, N. Jha, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Memory binding for performance optimization of control-flow intensive behaviors

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems

Niraj K. Jha, Ganesh Lakshminarayana, Bharat P. Dave, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Power management in high-level synthesis

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips

Sujit Dey, Ganesh Lakshminarayana, Anand Raghunathan, 2000, Proceedings 37th Design Automation Conference.

Transforming control-flow intensive designs to facilitate power management

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1998, ICCAD.

Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Analysis of power dissipation in embedded systems using real-time operating systems

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testing of core-based systems-on-a-chip

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power analysis of embedded operating systems

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2000, Proceedings 37th Design Automation Conference.

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The LOTTERYBUS on-chip communication architecture

Ganesh Lakshminarayana, Anand Raghunathan, Kanishka Lahiri, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast high-level power estimation for control-flow intensive designs

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

High-level synthesis of low-power control-flow intensive circuits

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

IMPACT: A high-level synthesis system for low power control-flow intensive circuits

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 1998, Proceedings Design, Automation and Test in Europe.

A power management methodology for high-level synthesis

Sujit Dey, Niraj K. Jha, Ganesh Lakshminarayana, 1998, Proceedings Eleventh International Conference on VLSI Design.

Memory binding for performance optimization of control-flow intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, Kamal S. Khouri, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions

Niraj K. Jha, Ganesh Lakshminarayana, N. Jha, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2000, IEEE Trans. Computers.

Input space-adaptive optimization for embedded-software synthesis

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optimizing public-key encryption for wireless clients

Srivaths Ravi, Ganesh Lakshminarayana, Anand Raghunathan, 2002, 2002 IEEE International Conference on Communications. Conference Proceedings. ICC 2002 (Cat. No.02CH37333).

TAO: regular expression based high-level testability analysis and optimization

Srivaths Ravi, Niraj K. Jha, Ganesh Lakshminarayana, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Integrating variable-latency components into high-level synthesis

Srivaths Ravi, Ganesh Lakshminarayana, Vijay Raghunathan, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs

Ganesh Lakshminarayana, Anand Raghunathan, Kanishka Lahiri, 2001, DAC '01.

Input space adaptive design: a high-level methodology for optimizing energy and performance

Niraj K. Jha, Ganesh Lakshminarayana, Anand Raghunathan, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-level synthesis with variable-latency components

Srivaths Ravi, Ganesh Lakshminarayana, Vijay Raghunathan, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.