Shai Rotem

RAPPID: an asynchronous instruction length decoder

Ran Ginosar, Peter A. Beerel, Shai Rotem, 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

An asynchronous instruction length decoder

Ran Ginosar, Peter A. Beerel, Shai Rotem, 2001, IEEE J. Solid State Circuits.

Coordinated transformations for high-level synthesis of high performance microprocessor blocks

Nikil D. Dutt, Shai Rotem, Rajesh K. Gupta, 2002, DAC '02.

CAD directions for high performance asynchronous circuits

Ran Ginosar, Shai Rotem, Kenneth S. Stevens, 1999, DAC '99.

TAO: two-level atomicity for dynamic binary optimizations

Wei Liu, Cheng Wang, Shai Rotem, 2010, CGO '10.

Relative timing

Ran Ginosar, Shai Rotem, Kenneth S. Stevens, 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Average-case optimized technology mapping of one-hot domino circuits

Ran Ginosar, Peter A. Beerel, Shai Rotem, 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

CA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoder

Shai Rotem, Kenneth S. Stevens, Marly Roncken, 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).