Subramanian S. Iyer

发表

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Subramanian S. Iyer, G. Freeman, C. Brodsky, 2011, IBM J. Res. Dev..

Three-dimensional wafer scale integration for ultra-large-scale cognitive systems

Subramanian S. Iyer, Zhe Wan, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

Richard E. Matick, Subramanian S. Iyer, Paul C. Parries, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Reliability Evaluation of Silicon Interconnect Fabric Technology

Subramanian S. Iyer, Boris Vaisband, Kannan K. Thankappan, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Subramanian S. Iyer, Toshiaki Kirihata, Donald W. Plass, 2016, IEEE Journal of Solid-State Circuits.

Advanced Packaging and Heterogeneous Integration to Reboot Computing

Puneet Gupta, Saptadeep Pal, Subramanian S. Iyer, 2017, 2017 IEEE International Conference on Rebooting Computing (ICRC).

Silicon stress: technical perspective

Subramanian S. Iyer, 2014, CACM.

Architecting Waferscale Processors - A GPU Case Study

Puneet Gupta, Rakesh Kumar, Saptadeep Pal, 2019, 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Communication Considerations for Silicon Interconnect Fabric

Subramanian S. Iyer, Boris Vaisband, 2019, 2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

(Invited) From Deep Trenches to Sky Scrapers - On some issues Concerning the Technology and Design of Embedded DRAM and Three Dimensional Integrated Circuits Form Memory Applications

Subramanian S. Iyer, 2010 .

Monolithic three-dimensional integration for memory scaling and neuromorphic computing

Subramanian S. Iyer, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

Puneet Gupta, Saptadeep Pal, Subramanian S. Iyer, 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

Subramanian S. Iyer, Srivatsan Chellappa, Toshiaki Kirihata, 2013, IEEE Journal of Solid-State Circuits.

Three-Dimensional Integration: A Tutorial for Designers

Subramanian S. Iyer, Toshiaki Kirihata, S. Iyer, 2015, IEEE Solid-State Circuits Magazine.

Goodbye, motherboard. Bare chiplets bonded to silicon will make computers smaller and more powerful: Hello, silicon-interconnect fabric

Subramanian S. Iyer, Puneet Gupta, Puneet Gupta, 2019, IEEE Spectrum.

Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation

Wei Kong, Subramanian S. Iyer, Paul C. Parries, 2008, 2008 IEEE International Test Conference.

Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM

Subramanian S. Iyer, Toshiaki Kirihata, Alberto Cestero, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems

Subramanian S. Iyer, Boris Vaisband, SivaChandra Jangam, 2019, IBM J. Res. Dev..

Process Integration for FlexTrateTM

Tetsu Tanaka, Hisashi Kino, Subramanian S. Iyer, 2018, 2018 International Flexible Electronics Technology Conference (IFETC).

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

Xiang Chen, Subramanian S. Iyer, Toshiaki Kirihata, 2007, 2007 IEEE Custom Integrated Circuits Conference.

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)

Mau-Chung Frank Chang, Li Du, Boyu Hu, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optimisation of CoSi2 Based Electrical Fuses for Redundancy Implementation in Sub-0.13 μm Embedded DRAM Applications

Subramanian S. Iyer, Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer, 2000 .

Heterogeneous Integration for Performance and Scaling

Subramanian S. Iyer, S. Iyer, 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

Ming Yin, Balaji Jayaraman, Subramanian S. Iyer, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS

Brian Reed, Subramanian S. Iyer, Toshiaki Kirihata, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

Richard E. Matick, Subramanian S. Iyer, Paul C. Parries, 2008, IEEE Journal of Solid-State Circuits.

Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications

X. Chen, Subramanian S. Iyer, Toshiaki Kirihata, 2015, 2015 IEEE International Reliability Physics Symposium.

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond

Bernhard Wunder, Balaji Jayaraman, Subramanian S. Iyer, 2012, 2012 IEEE International Conference on IC Design & Technology.

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Subramanian S. Iyer, Toshiaki Kirihata, Alberto Cestero, 2013, IEEE Journal of Solid-State Circuits.

Network on interconnect fabric

Subramanian S. Iyer, Boris Vaisband, Adeel Ahmad Bajwa, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Fine-Pitch Integration Technology for Cognitive System Scaling

Subramanian S. Iyer, Zhe Wan, 2018 .

Unsupervised Learning Using Charge-Trap Transistors

Subramanian S. Iyer, Xuefeng Gu, S. Iyer, 2017, IEEE Electron Device Letters.

Integrated neural interfaces

Jason Silver, Subramanian S. Iyer, Ross M. Walker, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Subramanian S. Iyer, Jason C. S. Woo, Faraz Khan, 2017, IEEE Electron Device Letters.

Reliability challenges in advance packaging

Subramanian S. Iyer, Adeel Ahmad Bajwa, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability

Fen Chen, J. Liu, Subramanian S. Iyer, 2015, 2015 IEEE International Reliability Physics Symposium.

Performance-based metrology of critical device performance parameters for in-line non-contact high-density intra-die monitor/control on a 32nm SOI advanced logic product platform

Xiaojun Yu, Mario M. Pelella, Subramanian S. Iyer, 2013, Advanced Lithography.

Heterogeneous SoCs

Subramanian S. Iyer, 2017, VLSI-DAT.

Optimized Power Delivery for 3D IC Technology Using Grind Side Redistribution Layers

Subramanian S. Iyer, Prakash Periasamy, Menglu Li, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Three Dimensional integration - Considerations for memory applications

John E. Barth, Subramanian S. Iyer, Toshiaki Kirihata, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Global and semi-global communication on Si-IF

Subramanian S. Iyer, Boris Vaisband, 2019, NOCS.

Packaging without the Package - A More Holistic Moore's Law

Subramanian S. Iyer, 2017 .

A Case for Packageless Processors

Puneet Gupta, Rakesh Kumar, Saptadeep Pal, 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Embedded DRAM: Technology platform for the Blue Gene/L chip

John E. Barth, James P. Rice, Subramanian S. Iyer, 2005, IBM J. Res. Dev..

Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines pdf

Tianyi Wang, Vwani P. Roychowdhury, Subramanian S. Iyer, 2020, ACM J. Emerg. Technol. Comput. Syst..

A Signaling Figure of Merit (s-FoM) for Advanced Packaging

Subramanian S. Iyer, SivaChandra Jangam, 2020, IEEE Transactions on Components, Packaging and Manufacturing Technology.

The Impact of Proton-Induced Single Events on Image Classification in a Neuromorphic Computing Architecture

Ronald D. Schrimpf, Subramanian S. Iyer, Michael L. Alles, 2020, IEEE Transactions on Nuclear Science.

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

Ming Yin, Balaji Jayaraman, Subramanian S. Iyer, 2018, IEEE Journal of Solid-State Circuits.

3D integration review

Subramanian S. Iyer, Mukta G. Farooq, M. Farooq, 2011, Science China Information Sciences.

Heterogeneous Integration using the Silicon Interconnect Fabric

Subramanian S. Iyer, 2018, 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM).

Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration

Arvind Kumar, Winfried W. Wilcke, Subramanian S. Iyer, 2017, ACM J. Emerg. Technol. Comput. Syst..

“FlexTrate ^TM” — Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Using FOWLP

Saptadeep Pal, Takafumi Fukushima, Subramanian S. Iyer, 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding

Saptadeep Pal, Takafumi Fukushima, Subramanian S. Iyer, 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).