Naftali E. Lustig

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Subramanian S. Iyer, G. Freeman, C. Brodsky, 2011, IBM J. Res. Dev..

Wafer Scale Cu Plating Process Optimization for Defectivity Improvement

Qiang Huang, Naftali E. Lustig, Shafaat Ahmed, 2014 .

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Suhwan Kim, Keith A. Jenkins, Jean-Olivier Plouchart, 2003, IBM J. Res. Dev..

Silicon containing polymer in applications for 193 nm high NA lithography processes

Karen Petrillo, Allen H. Gabor, Naftali E. Lustig, 2006, SPIE Advanced Lithography.

First microprocessors with immersion lithography

Todd C. Bailey, Naftali E. Lustig, Karen Petrillo, 2004, SPIE Advanced Lithography.

Trilayer Development for 193 nm Immersion Lithography

Dario L. Goldfarb, Naftali E. Lustig, Sean D. Burns, 2007 .

A high performance 0.13 /spl mu/m copper BEOL technology with low-k dielectric

Daniel C. Edelstein, Sampath Purushothaman, Alina Deutsch, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).