Shreesh Narasimha

发表

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Subramanian S. Iyer, G. Freeman, C. Brodsky, 2011, IBM J. Res. Dev..

Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challenges

Kai Zhao, Fen Chen, Xiao Hu Liu, 2015, Microelectron. Reliab..

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Suhwan Kim, Keith A. Jenkins, Jean-Olivier Plouchart, 2003, IBM J. Res. Dev..

Optimization of silicon technology for the IBM System z9

Daniel C. Edelstein, Mukesh Khare, Gary B. Bronner, 2007, IBM J. Res. Dev..

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

G. Freeman, Shreesh Narasimha, James P. Norum, 2015, IBM J. Res. Dev..