Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate length

The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 mu m. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S-factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found. >

[1]  Jason C. S. Woo,et al.  Two-dimensional analytic modeling of very thin SOI MOSFETs , 1990 .

[2]  J. Colinge Subthreshold slope of thin-film SOI MOSFET's , 1986, IEEE Electron Device Letters.

[3]  H. Tango,et al.  Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film , 1989 .

[4]  K. Throngnumchai,et al.  Modeling of 0.1-µm MOSFET on SOI structure using Monte Carlo simulation technique , 1986, IEEE Transactions on Electron Devices.

[5]  D. Wouters,et al.  Subthreshold slope in thin-film SOI MOSFETs , 1990 .

[6]  Y. Omura,et al.  0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer , 1991 .

[7]  K. K. Young Analysis of conduction in fully depleted SOI MOSFETs , 1989 .

[8]  T. Sekigawa,et al.  Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate , 1984 .

[9]  K. Tokunaga,et al.  Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors , 1988, IEEE Electron Device Letters.

[10]  J.-P. Colinge,et al.  Hot-electron effects in Silicon-on-insulator n-channel MOSFET's , 1987, IEEE Transactions on Electron Devices.

[11]  Gerard Ghibaudo,et al.  Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs , 1990 .

[12]  Jason C. S. Woo,et al.  Design and performance of submicron MOSFETs on ultra-thin SOI for room temperature and cryogenic operation , 1988, Technical Digest., International Electron Devices Meeting.

[13]  K. K. Young Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[14]  T. Nishida,et al.  Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's) , 1992, IEEE Electron Device Letters.

[15]  J. B. McKitterick,et al.  An analytic model for thin SOI transistors , 1989 .

[16]  D. Moy,et al.  Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devices , 1987, 1987 International Electron Devices Meeting.