High Real-Time Design of Digital Pulse Compression Based on FPGA

Because of the poor real-time performance of in-place fast Fourier transforms, a reconfigurable radix-4 FFT processor is studied and designed, which is based on decimation-in-time and single floating-point computation. The proposed method adopts “pipeline and parallel” structure for accessing multiple memories to improve the FFT processing speed, and then it is applied to digital pulse compression. The experimental result shows that the proposed FFT based on radix-4 computation can implement digital pulse compression rapidly under no adding hardware resources. The proposed method can be also applied to other radix FFTs.

[1]  Myung Hoon Sunwoo,et al.  New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Hui Li,et al.  Design of an IPv4/IPv6 Translator Based on SOPC Technology , 2008, 2008 IEEE International Conference on Networking, Sensing and Control.

[3]  He Chen,et al.  An efficient design of high-accuracy and low-cost FFT , 2013 .

[4]  Chen He.  Implementation of Digital Pulse Compression System Based on FPGA , 2010 .

[5]  Pao-Ann Hsiung,et al.  A low-power 64-point pipeline FFT/IFFT processor for OFDM applications , 2011, IEEE Transactions on Consumer Electronics.

[6]  He Chen,et al.  An improved constant coefficient multiplication algorithm based on cascaded adder graph , 2013, Science China Information Sciences.

[7]  Long Teng,et al.  A high-speed real-time digital pulse compression system based on TMS320C6201 , 2001, 2001 CIE International Conference on Radar Proceedings (Cat No.01TH8559).

[8]  Jeffrey O. Coleman.  Cascaded coefficient number systems lead to FIR filters of striking computational efficiency , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[9]  Wei Wang,et al.  An Overview to FPGA Device Design Technologies , 2010 .

[10]  J.K. Kayani,et al.  Digital Implementation of Pulse Compression Technique for X-band Radar , 2007, 2007 International Bhurban Conference on Applied Sciences & Technology.

[11]  Yi Deng,et al.  Simplified addressing scheme for mixed radix FFT algorithms , 2014, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[12]  Huang Shi-tan.  A strategy of address generating for Programmable high throughout FFT processor , 2009 .

[13]  Han Yue-qiu.  A Fast Address Generation Scheme for FFT Processor , 2006 .

[14]  He Chen,et al.  A novel conflict-free parallel memory access scheme for FFT constant geometry architectures , 2013, Science China Information Sciences.