The influence of high resistivity substrates on CMOS latchup robustness

This paper demonstrates latchup results in a 50 Omega-cm substrate wafer in a 0.13-mum technology. Latchup evaluation will evaluate and compare a 10 Omega-cm and a 50 Omega-cm substrate wafer on the NPN bipolar current gain, beta<sub>npn</sub>, PNP bipolar current gain, beta<sub>pnp,</sub>, the bipolar current gain product, beta<sub>pnp</sub>beta<sub>npn</sub>, undershoot, and overshoot phenomena.

[1]  Steven H. Voldman.  A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup , 2005, Microelectron. Reliab..

[2]  A. Ochoa,et al.  An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process , 1978, 1978 International Electron Devices Meeting.

[3]  A. Watson,et al.  The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS silicon germanium technology , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[4]  T. Nakamura,et al.  Latch-up immunity against noise pulses in a CMOS double well structure , 1983, 1983 International Electron Devices Meeting.

[5]  E. Gebreselasie,et al.  The influence of a silicon dioxide-filled trench isolation structure and implanted sub-collector on latchup robustness , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[6]  J. Slinkman,et al.  Retrograde well and epitaxial thickness optimization for shallow- and deep-trench collar merged isolation and node trench SPT DRAM cell and CMOS logic technology , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[7]  Charvaka Duvvury,et al.  Impact of scaling on the high current behavior of RF CMOS technology , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[8]  L. Lanzerotti,et al.  The influence of heavily doped buried layer implants on electrostatic discharge (ESD), latchup, and a silicon germanium heterojunction bipolar transistor in a BiCMOS SiGe technology , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[9]  A. Watson,et al.  The effect of deep trench and sub-collector on the latchup robustness in BiCMOS silicon germanium technology , 2004, Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting.

[10]  R. Troutman,et al.  Epitaxial layer enhancement of n-well guard rings for CMOS circuits , 1983, IEEE Electron Device Letters.

[11]  D. K. Nichols,et al.  Latchup in CMOS Integrated Circuits , 1985 .

[12]  S.H. Voldman.  The effect of deep trench isolation, trench isolation and sub-collector doping on the electrostatic discharge (ESD) robustness of radio frequency (RF) ESD STI-bound P+/N-well diodes in BiCMOS silicon germanium technology , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[13]  W. Morris,et al.  Latchup in CMOS , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[14]  S.H. Voldman,et al.  Latchup and the domino effect , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[15]  Donald B. Estreich.  The physics and modeling of latch-up and CMOS integrated circuits , 1980 .

[16]  Steven H. Voldman,et al.  MeV implants boost device design , 1995 .

[17]  C. Duvvury,et al.  Latch-up in 65nm CMOS technology: a scaling perspective , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[18]  Ronald R. Troutman,et al.  Latchup in CMOS Technology: The Problem and Its Cure , 1986 .

[19]  C. Duvvury,et al.  Impact of scaling on the high current behavior of RF CMOS technology , 2004, IEEE Transactions on Device and Materials Reliability.

[20]  S. Voldman.  ESD: Physics and Devices , 2004 .

[21]  J. Harter,et al.  Comparison of latch-up in p- and n-well CMOS circuits , 1983, 1983 International Electron Devices Meeting.