Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
暂无分享,去创建一个
[1] P. Hazucha,et al. Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .
[2] D. Rossi,et al. Latch Susceptibility to Transient Faults and New Hardening Approach , 2007, IEEE Transactions on Computers.
[3] Nihar R. Mahapatra,et al. Combining error masking and error detection plus recovery to combat soft errors in static CMOS circuits , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).
[4] Christos A. Papachristou,et al. Node sensitivity analysis for soft errors in CMOS logic , 2005, IEEE International Conference on Test, 2005..
[5] E. L. Lawler,et al. Branch-and-Bound Methods: A Survey , 1966, Oper. Res..
[6] Vishwani D. Agrawal. Low-power design by hazard filtering , 1997, Proceedings Tenth International Conference on VLSI Design.
[7] Kenneth P. Rodbell,et al. Single-Event Upsets in Microelectronics: Fundamental Physics and Issues , 2003 .
[8] Hideo Ito,et al. Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger , 2008, J. Electron. Test..
[9] D. Sylvester,et al. Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[10] David Blaauw,et al. Soft error reduction in combinational logic using gate resizing and flipflop selection , 2006, ICCAD.
[11] Stephen P. Boyd,et al. Digital Circuit Optimization via Geometric Programming , 2005, Oper. Res..
[12] Andreas G. Veneris,et al. Seamless Integration of SER in Rewiring-Based Design Space Exploration , 2006, 2006 IEEE International Test Conference.
[13] Quming Zhou,et al. Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[14] Stephen P. Boyd,et al. A tutorial on geometric programming , 2007, Optimization and Engineering.
[15] Quming Zhou,et al. Transistor sizing for radiation hardening , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.
[16] Kartik Mohanram,et al. Cost-effective radiation hardening technique for combinational logic , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[17] Abhijit Chatterjee,et al. On transistor level gate sizing for increased robustness to transient faults , 2005, 11th IEEE International On-Line Testing Symposium.
[18] David Blaauw,et al. Gate-level mitigation techniques for neutron-induced soft error rate , 2005, Sixth international symposium on quality electronic design (isqed'05).
[19] Robert Baumann,et al. Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.
[20] Ming Zhang,et al. Combinational Logic Soft Error Correction , 2006, 2006 IEEE International Test Conference.
[21] Lorena Anghel,et al. On implementing a soft error hardening technique by using an automatic layout generator: case study , 2005, 11th IEEE International On-Line Testing Symposium.
[22] S. Vangal,et al. Selective node engineering for chip-level soft error rate improvement [in CMOS] , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[23] Changhong Dai,et al. Circuit-level modeling of soft errors in integrated circuits , 2005, IEEE Transactions on Device and Materials Reliability.
[24] Michael Nicolaidis. Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[25] S. Yang,et al. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .
[26] Nur A. Touba,et al. Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[27] Diana Marculescu,et al. Soft error rate reduction using redundancy addition and removal , 2008, 2008 Asia and South Pacific Design Automation Conference.
[28] N. Seifert,et al. Robust system design with built-in soft-error resilience , 2005, Computer.
[29] Kartik Mohanram,et al. Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits , 2008, 2008 13th European Test Symposium.
[30] Abhijit Chatterjee,et al. Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits , 2005, 11th IEEE International On-Line Testing Symposium.
[31] Lloyd W. Massengill,et al. Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .
[32] P. Eaton,et al. Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[33] Kartik Mohanram,et al. Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[34] Gwan S. Choi,et al. A design approach for radiation-hard digital electronics , 2006, 2006 43rd ACM/IEEE Design Automation Conference.