Vector replacement to improve static-test compaction forsynchronous sequential circuits

Static-test compaction procedures for synchronous sequential circuits may saturate and be unable to further reduce the test-sequence length before the test length reaches its minimum value, resulting in test sequences that may be longer than necessary. We propose a method to take a static-compaction procedure out of saturation and allow it to continue reducing the test-sequence length. The proposed method is based on the replacement of test vectors in the test sequence every time the compaction procedure reaches saturation. Test-vector replacement is done such that the fault coverage of the sequence is maintained. Experimental results using an effective static-compaction procedure demonstrate that reductions in test length can be obtained by the proposed vector replacement method.

[1]  Irith Pomeranz,et al.  Vector restoration based static compaction of test sequences for synchronous sequential circuits , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[2]  Michael S. Hsiao,et al.  Fast Static Compaction Algorithms for Sequential Circuit Test Vectors , 1999, IEEE Trans. Computers.

[3]  Michael S. Hsiao,et al.  Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[4]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[5]  Michael S. Hsiao,et al.  Fast algorithms for static compaction of sequential circuit test vectors , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[6]  Paolo Prinetto,et al.  New static compaction techniques of test sequences for sequential circuits , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[7]  Enrico Macii,et al.  A structural approach to state space decomposition for approximate reachability analysis , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[8]  Kenneth L. McMillan,et al.  Approximation and decomposition of binary decision diagrams , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[9]  Kewal K. Saluja,et al.  Random pattern testing for sequential circuits revisited , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

[10]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[11]  Michael S. Hsiao,et al.  State relaxation based subsequence removal for fast static compaction in sequential circuits , 1998, Proceedings Design, Automation and Test in Europe.

[12]  Irith Pomeranz,et al.  On static compaction of test sequences for synchronous sequential circuits , 1996, DAC '96.

[13]  A. Richard Newton,et al.  Implicit manipulation of equivalence classes using binary decision diagrams , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[14]  Irith Pomeranz,et al.  An approach for improving the levels of compaction achieved by vector omission , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[15]  Byungse So Time-efficient automatic test pattern generation systems , 1994 .

[16]  Tiziano Villa,et al.  VIS: A System for Verification and Synthesis , 1996, CAV.

[17]  Kavita Ravi,et al.  High-density reachability analysis , 1995, ICCAD.

[18]  Robert K. Brayton,et al.  Heuristic Minimization of BDDs Using Don't Cares , 1994, 31st Design Automation Conference.

[19]  Adnan Aziz,et al.  Enhancing simulation with BDDs and ATPG , 1999, DAC '99.

[20]  Janak H. Patel,et al.  Compaction of ATPG-generated test sequences for sequential circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[21]  Irith Pomeranz,et al.  On the effects of test compaction on defect coverage , 1996, Proceedings of 14th VLSI Test Symposium.