A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

[1]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[2]  B. Vasquez,et al.  The Promise of Known-good-die Technologies , 1994, Proceedings of the International Conference on Multichip Modules.

[3]  M. Bohr,et al.  A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[4]  R.R. Tummala,et al.  Packaging: past, present and future , 2005, 2005 6th International Conference on Electronic Packaging Technology.

[5]  E.R. St Pierre,et al.  Reliability improvement and burn in optimization through the use of die level predictive modeling , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[6]  Kazumasa Yanagisawa,et al.  A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit , 2002 .

[7]  T. Furuyama,et al.  Wafer burn-in (WBI) technology for RAM's , 1993, Proceedings of IEEE International Electron Devices Meeting.

[8]  Y. Kobayashi,et al.  A Novel Cu Electrical Fuse Structure and Blowing Scheme Utilizing Crack-Assisted Mode for 90-45nm-Node and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[9]  K. Ishibashi,et al.  A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits , 2007, IEEE Journal of Solid-State Circuits.

[10]  J.W. Miller,et al.  Wafer Level IC Burn-in As A Step Towards Bir , 1992, International Report on Wafer Level Reliability Workshop.

[11]  Steven F. Oakland,et al.  On-chip repair and an ATE independent fusing methodology , 2002, Proceedings. International Test Conference.

[12]  W. C. Riordan,et al.  Microprocessor reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[13]  Jinseok Lee,et al.  Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[14]  Russell B. Miller,et al.  Unit level predicted yield: a method of identifying high defect density die at wafer sort , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[15]  K. Ishibashi,et al.  A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[16]  Adit D. Singh,et al.  Redundancy implications for early-life reliability: experimental verification of an integrated yield-reliability model , 2002, Proceedings. International Test Conference.

[17]  S.K. Iyer,et al.  Electrically programmable fuse (eFUSE) using electromigration in silicides , 2002, IEEE Electron Device Letters.

[18]  K. Nii,et al.  90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique , 2006, IEEE Journal of Solid-State Circuits.