Parallel media processors for the billion-transistor era

This paper describes the challenges presented by single-chip parallel media processors (PMPs). These machines integrate multiple parallel function units, instruction execution, and memory hierarchies on a single chip. The combination of programmability and high performance on data parallelism is necessary to meet the demands of next-generation multimedia applications. Many research issues must be solved to realize the full potential of programmable media processors. This paper provides both a survey of research trends and issues in architecture and compiler design for programmable media processors, and an exploration of the potential performance of media processors over the next decade.

[1]  Syed A. Rizvi.  Analyzing the tolerance and controls on critical dimensions and overlays as prescribed by the National Technology Roadmap for Semiconductors , 1997, Other Conferences.

[2]  Angelos Bilas,et al.  Real-time parallel MPEG-2 decoding in software , 1997, Proceedings 11th International Parallel Processing Symposium.

[3]  Wayne Wolf,et al.  Study of cache system in video signal processors , 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

[4]  Thomas M. Conte,et al.  Instruction scheduling and fetch mechanisms for clustered vliw processors , 1998 .

[5]  Mary W. Hall,et al.  Detecting Coarse - Grain Parallelism Using an Interprocedural Parallelizing Compiler , 1995, Proceedings of the IEEE/ACM SC95 Conference.

[6]  Michael J. Flynn,et al.  A comparison of hardware prefetching techniques for multimedia benchmarks , 1996, Proceedings of the Third IEEE International Conference on Multimedia Computing and Systems.

[7]  Wayne Wolf,et al.  Parallel Architectures for Programmable Video Signal Processing , 2001 .

[8]  Brucek Khailany,et al.  Media processing using streams , 1998, Electronic Imaging.

[9]  Rudolf Eigenmann,et al.  Automatic program parallelization , 1993, Proc. IEEE.

[10]  Andrew Wolfe,et al.  Datapath design for a VLIW video signal processor , 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

[11]  Peter Pirsch,et al.  An Algorithm-Hardware-System Approach to VLIW Multimedia Processors , 1998, J. VLSI Signal Process..

[12]  A PattersonDavid,et al.  A New Direction for Computer Architecture Research , 1998 .

[13]  Andrew Wolfe,et al.  Available parallelism in video applications , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[14]  Wayne H. Wolf,et al.  Design study of shared memory in VLIW video signal processors , 1998, Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192).

[15]  Manish Gupta,et al.  Interaction Between Data Parallel Compilation and Data Transfer and Storage Cost Minimization for Multimedia Applications , 1999, Euro-Par.

[16]  Christoforos E. Kozyrakis,et al.  A New Direction for Computer Architecture Research , 1998, Computer.

[17]  Yiqing Liang,et al.  A digital video library on the World Wide Web , 1997, MULTIMEDIA '96.

[18]  Alexandre E. Eichenberger,et al.  Effective cluster assignment for modulo scheduling , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[19]  Wayne H. Wolf,et al.  Trace-driven studies of VLIW video signal processors , 1998, SPAA '98.

[20]  Bede Liu,et al.  Understanding multimedia application characteristics for designing programmable media processors , 1998, Electronic Imaging.

[21]  Sun-Yuan Kung,et al.  Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation , 1998, J. VLSI Signal Process..