Some recent advances in software and hardware logic simulation
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[1] Srinivas Devadas,et al. Boolean satisfiability and equivalence checking using general Binary Decision Diagrams , 1992, Integr..
[2] Michael Miller,et al. Emulation verification of the Motorola 68060 , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[3] Katherine A. Yelick,et al. Parallel timing simulation on a distributed memory multiprocessor , 1993, ICCAD.
[4] Rajeev Murgai,et al. Logic synthesis for a single large look-up table , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[5] Sharad Malik,et al. Fast functional simulation using branching programs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[6] Robert K. Brayton,et al. Logic Synthesis for Field-Programmable Gate Arrays , 1995 .
[7] Premachandran R. Menon,et al. A Logic Simulation Machine , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[9] Masahiro Fujita,et al. Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[10] Tom Blank,et al. Parallel logic simulation on general purpose machines , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[11] Alexander Saldanha,et al. Fast discrete function evaluation using decision diagrams , 1995, ICCAD.
[12] Jeffrey M. Arnold,et al. PARALLEL SIMULATION OF DIGITAL LSI CIRCUITS , 1985 .
[13] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[14] Barry K. Rosen,et al. HSS--A High-Speed Simulator , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] David R. Jefferson,et al. Virtual time , 1985, ICPP.
[16] Nobuhiko Koike,et al. HAL; A Block Level Hardware Logic Simulator , 1983, 20th Design Automation Conference Proceedings.
[17] Ernst G. Ulrich. Exclusive simulation of activity in digital networks , 1969, CACM.
[18] A.L. Sangiovanni-Vincentelli,et al. Fast discrete function evaluation using decision diagrams , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[19] Saburo Muroga,et al. Binary Decision Diagrams , 2000, The VLSI Handbook.
[20] Jonathan Rose,et al. Chortle-crf: fast technology mapping for lookup table-based FPGAs , 1991, 28th ACM/IEEE Design Automation Conference.
[21] Fumiyasu Hirose,et al. Simulation processor "SP" , 1989, Syst. Comput. Jpn..
[22] 藤田 昌宏,et al. Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams , 1988 .
[23] K. Mani Chandy,et al. Asynchronous distributed simulation via a sequence of parallel computations , 1981, CACM.
[24] Eduard Cerny,et al. Simulation of MOS Circuits by Decision Diagrams , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[25] Stephen A. Szygenda. TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic , 1972, DAC '72.
[26] Aarti Gupta,et al. Formal hardware verification methods: A survey , 1992, Formal Methods Syst. Des..
[27] M.M. Denneau. The Yorktown Simulation Engine , 1982, 19th Design Automation Conference.
[28] Jacob A. Abraham,et al. IBDDs: an efficient functional representation for digital circuits , 1992, [1992] Proceedings The European Conference on Design Automation.