MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization

Although recent advances in resistive random access memory (ReRAM)-based accelerator designs for deep convolutional neural networks (CNNs) offer energy-efficiency improvements over CMOS-based accelerators, they have a large number of energy consuming data transactions. In this paper, we propose MAX², a multi-tile ReRAM accelerator framework for supporting multiple CNN topologies, that maximizes on-chip data reuse and reduces on-chip bandwidth to minimize energy consumption due to data movement. Building upon the fact that a large filter can be built with a stack of smaller (<inline-formula> <tex-math notation="LaTeX">$3\times 3$ </tex-math></inline-formula>) filters, we design every tile with nine processing elements (PEs). Each PE consists of multiple ReRAM subarrays to compute the dot product. The PEs operate in a systolic fashion, thereby maximizing input feature map reuse and minimizing interconnection cost. MAX² chooses the data size granularity in the systolic array in conjunction with weight duplication to achieve very high area utilization without requiring additional peripheral circuits. We provide a detailed energy and area breakdown of each component at the PE level, tile level, and system level. The system-level evaluation in 32-nm node on several VGG-network benchmarks shows that the MAX² can improve computation efficiency (TOPs/s/mm²) by <inline-formula> <tex-math notation="LaTeX">$2.5\times $ </tex-math></inline-formula> and energy efficiency (TOPs/s/W) by <inline-formula> <tex-math notation="LaTeX">$5.2\times $ </tex-math></inline-formula> compared with a state-of-the-art ReRAM-based accelerator.