Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer

A noise-shaped two-step ADC is presented in this paper. This ADC exploits residue feedback and a new capacitor/opamp sharing scheme to achieve high order noise shaping with minimal design complexity. The application of the proposed architecture in low power Delta-Sigma modulators is studied in this paper. A prototype ADC is fabricated in a 0.18 μm CMOS process. With a 1.56 MHz bandwidth (8x OSR), 2.6 mW analog power consumption, and 1.2 V analog supply voltage, the measured dynamic range and SNDR of this prototype IC are 78 dB and 75 dB.

[1]  A. L. Coban,et al.  Single-loop delta-sigma modulator with swing suppression , 1995 .

[2]  Todd L. Brooks,et al.  A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997 .

[3]  David H. Robertson,et al.  A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997, IEEE J. Solid State Circuits.

[4]  S. Lindfors.  A two-step quantization /spl Delta//spl Sigma/-modulator architecture with cascaded digital noise cancellation , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[5]  L. Longo,et al.  A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.

[6]  I. Fujimori,et al.  A 90 dB SNR, 2.5 MHz output rate ADC using cascaded multibit /spl Delta//spl Sigma/ modulation at 8x oversampling ratio , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[7]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[8]  Yongjie Cheng,et al.  A 4/sup th/ order single-loop delta-sigma ADC with 8-bit two-step flash quantization , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[9]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[10]  Walt Kester,et al.  The data conversion handbook , 2005 .

[11]  J. Paramesh,et al.  An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[12]  David J. Comer,et al.  Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  G.C. Temes,et al.  A Split 2-0 MASH with Dual Digital Error Correction , 2007, 2007 IEEE Symposium on VLSI Circuits.

[14]  Yong Ping Xu,et al.  A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[15]  Un-Ku Moon,et al.  Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[16]  G. Temes,et al.  Single-loop ΔΣ modulator with extended dynamic range , 2008 .

[17]  I-Ching Chen,et al.  A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-$\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[18]  D.A. Johns,et al.  A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator , 2009, IEEE Journal of Solid-State Circuits.

[19]  Koichi Hamashita,et al.  Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC , 2010, IEEE Journal of Solid-State Circuits.

[20]  O. Rajaee,et al.  A 1.2V, 78dB HDSP ADC with 3.1V input signal range , 2010, 2010 IEEE Asian Solid-State Circuits Conference.