The Perspectives of Silicon‐on‐Insulator Technologies for Cryogenic Applications

The potential and restrictions of cryogenic SOI technologies are reviewed. First the low temperature device operation, illustrated by extensive experimental data covering a broad temperature range down to liquid helium, is discussed in order to validate the theoretical models. Attention is given to the kink phenomenon, t ransient and hysteresis effects, the device breakdown and latch-up behavior, and the noise performance. Several design methodologies and technological modifications for eliminating the cryogenic artifacts are critically discussed. Alternative device concepts such as the twin-transistor structure and the gate-all-around concept are also addressed. Finally some considerations for digital and analog circuit applications are given in view of the future perspectives of cryogenic SOI CMOS technologies. For a long time it was believed that due to the lower process complexity and the strong efforts to reduce the material cost, si l icon-on-insulator (SOI) would be the leading complementary metal oxide semiconductor (CMOS) technology for devices with 0.5 ~m or lower feature size. However, the strong material improvements, resulting in low defect densities and higher minority carrier liietimes, in combination with the presence of parasitic bipolar effects seriously hampered the breakthrough of SOI for submicron technologies. Only the more recent trend to reduce the supply voltage and the implementation of techniques to improve the drain breakdown voltage 1 are giving SOI a new potential for becoming the driving technology for sub0.25 ~m CMOS. Appropriate scaling laws are developed for the deep submicron regime. 2 The strong potential of SOI for deep submicron technologies recently has been reviewed by Colinge. 3 The electrical performance considerably improves by using a partly depleted SOI technology compared to bulk CMOS, i.e., improved subthreshold slope, higher carrier mobilities, higher transconductance, less sensitive to shortchannel effects, and improved radiatio n hardness. 4 The potential drawbacks associated with floating body operation such as drain current kink and early breakdown can be overcome by using fully depleted devices. The hot-carrier degradation behavior of SOI devices is less clear and some contradictory results can be found in the literature. The SOI approach offers some technological means for improvement, such as, e.g., the use of fully depleted devices or n-type accumulation mode operation. However, the reduction of the supply voltage is making hot carrier phenomena less problematic. The main difficulty in making a comparison between different technologies is that one must compare devices with similar electrical parameters such as e.g., threshold voltage and saturation current. The electrical SOI CMOS performance is also linked to the material properties, so that one must differentiate between SOI layers produced by laser recrystallization, separation by implantation of oxygen (SIMOX), and wafer bonding bond and etchback silicon on insulator (BESOI), respectively. From the viewpoint of defect levels, SOI layer parameters control, and overall manufacturability, SIMOX and BESOI are far outstanding. For the moment SIMOX is dominating the market, while BESOI is increasingly gaining importance and becoming a strong competitor. For more than a decade, it has been recognized that low temperature device operation strongly improves the electrical performance of CMOS technologies. 5 The main advantages resulting from the cryogenic operation are improved speed performance due to the increase in carrier mobility and saturation velocity, reduction of the power dissipation as the subthreshold characteristics improve, improvement of the device reliability due to latch-up suppression and reduced electromigration, reduction of junc* Electrochemical Society Active Member. 2522 J. Electrochem. Soc., Vol. tion leakage allowing higher packing densities, and reduction of the interconnection resistance and capacitances leading to higher switching speeds. For liquid nitrogen operation these advantages have recently been reviewed. 6.7 As early as 1987, the first design and experimental technology for 0.i ~m transistors were reported. ~-I~ More recently, Mii et al. 11 obtained switching speeds as low as I0 ps/stage for 0.08 btm metal oxide semiconductor transistors (MOSTs) operating at 85 K and with a supply voltage of 1.5 V. Compared to the room temperature speed of 13 ps/stage this represents an improvement of about 25 %. For an optimized cryogenic 0.7 ~m CMOS technology, Henkels et al. 12 obtained for 85 K operation, a 25 ns row access time and 55 ns cycle time for a 4 Mbyte dynamic random access memory (DRAM) which is about three times faster compared to room temperature DRAMs. A straightforward approach for obtaining the optimum in device performance is to use a cryogenic SOl technology. Since the first report by Elewa et al. 13 on the electrical behavior of low temperature SOI MOS operation, several research teams became active in this field. This paper aims at a general overview of the cryogenic operation of SOI CMOS devices. A first Section presents insights into the device operation over a broad temperature range down to liquid helium. Special attention is given to the kink phenomenon, transient and hysteresis effects, breakdown voltage and latch-up sensitivity, low frequency noise behavior, and the subthreshold slope. A critical synthesis of the results, supported by extensive experimental data, is presented. A second Section outlines both design methodologies and technological modifications resulting in a suppression of the cryogenic artifacts. Advanced device concepts such as the gate-all-around (GAA) device and the twin-transistor structure are reviewed. Attention is also given to the potential use of accumulation mode devices, which are receiving a strong interest currently. General guidelines resulting in a n optimized cryogenic SOI CMOS technology are given. A third Section discusses some general considerations concerning the use of cryogenic SOI CMOS technologies for digital and analog applications. Finally, general conclusions are given on the future perspectives for the use of cryogenic SOI CMOS technologies. Cryogenic SOl Device Operation The use of si l icon-on-insulator devices originally was proposed as a cheaper alternative with comparable electrical performance as devices on silicon-on-sapphire (SOS) material, which for a long time was considered as the most mature material offering important advantages such as large area single-crystal films and full dielectric isolation with zero substrate bias capacitance. Therefore, some phenomena observed in SOI devices have been known for a long time. A typical example is the effects associated with the floating body operation of the devices, i.e., the kink phenomenon and the parasitic bipolar action for higher drain voltages, which were observed in 1975 by Tihanyi 141, No. 9, September 1994 9 The Electrochemical Society, Inc. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.122.253.228 Downloaded on 2015-05-21 to IP d. Electrochem. Soc., Vol. 141, No. 9, September 1994 9 The Electrochemical Society, Inc. 2523