Wafer bumping, assembly, and reliability assessment of μbumps with 5μm pads on 10μm pitch for 3D IC integration

In this study, ultra fine pitch Cu/Sn lead-free solder microbumps are investigated. Emphasis is placed on wafer bumping, assembly, and reliability of microbumps for 3D IC integration applications. The test vehicle consists of a chip (5mm × 5mm) with 3,200 pads. The pad size is 5μm in diameter and on 10μm pitch. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. The wet-etching process is used for the etching of seed layer. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. In addition, the shear test has been adopted to characterize the bump strength, which exceeds the specification. After wafer bumping and characterization of the microbumps, the Moore's law wafer is dicing into individual chips for chip-to-chip (C2C) bonding of the micro solder joints. The C2C bonding is a flux thermocompression process with a peak temperature of 260°C. The microstructure analyses reveal that the ultra fine pitch micro solder joint can be considered as an intermetallic compound (IMC) joint composed of Cu6Sn5 and a few residual solder compounds.

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