VLSI implementation of adders for high speed ALU

This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance of Central Processing Unit (CPU). In the past, thorough examination of the algorithms with the respect to particular technology has only been partially done. The merit of the new technology is to be evaluated by its ability to efficiently implement the computational algorithms. In the other words, the technology is developed with the aim to efficiently serve the computation. The reverse path; evaluating the merit of the algorithms should also be taken. Therefore, it is important to develop computational structures that fit well into the execution model of the processor and are optimized for the current technology. In such a case, optimization of the algorithms is performed globally across the critical path of its implementation. In this research article, we have simulated and synthesized the various adders like full adder, ripple carry adder, carry-look ahead adder, carry-skip adder, carry — select adder and carry-save adder by using VHDL and Xilinx ISE 9.2i. The simulated results are verified and the functionality of high speed adders and the parameters like area and speed is analyzed. Finally this paper concludes that the carry-save adder is the more efficient in speed and area consumption.