Solder joint reliability model vath modified Darveaux's equations for the micro smd wafer level-chip scale package family

Historically, energy-based solder fatigue lie models have been used primarily for PBGA or similar package configurations. In this paper, we extend the energy-based method to newly emerged Wafer Level, Chip Scale Package (WL-CSP). National Semiconductor’s micro SMD package family was chosen as the test vehicle. Among all energybased methods, Darveaux’s model is arguably the most popular one due to its well-documented good correlation with the actual tests. To maintain consistency in results, Darveaux suggested that the solder joint be meshed such that the element size in its height direction has fixed value. However, we found in our study that Darveaux’s model faired poorly in capturing the package fatigue life, even though the mesh size issue was carefully addressed. In view of the drastic difference in solder ball size between WL-CSP and PBGA, on which Darveaux’s model is based, we argue that in addition to the element size in the solder height direction, the f~te element calculation of inelastic dissipation may also depend on other meshing parameters, which may vary depending on the specific geometry of the solder bump. Consequently, we proposed a revised empirical equation to calculate the package fatigue life for micro SMD. The new equation is derived from correlating the simulation results with the test data. We also demonstrated that the new equation was capable of achieving a similar accuracy level as compared with Darveaux’s model for PBGA packages. The study also provided for the first time a good parametric model scalable to larger micro Sh4D VO count. In addition, the impact of different modeling schemes was also evaluated in terms of their accuracy and eficiency.