The Paralyzer: Ivtran's Parallelism Analyzer and Synthesizer

The ILLIAC IV Fortran compiler's Parallelism Analyzer and Synthesizer (mnemonicized as the Paralyzer) detects computations in Fortran DO loops which can be performed in parallel. It is a step of the compiling process which lies between source language parsing and target code generation, and as such can be considered as a high-level optimization step specific to the ILLIAC architecture. The Paralyzer performs its transformations within the Intermediate Language tables of the compiler. The parallel execution constructs introduced into the user's program are those which can be expressed in the extended Fortran language, IVTRAN, the source language of the compiler [1]. With a decompiler from the Intermediate Language to IVTRAN source, the Paralyzer can act as a source-to-source translater. Some pertinent characteristics of the ILLIAC IV motivate the parallelism detection methods employed by the Paralyzer. ILLIAC is in the general class of parallel processors known as array processors. That is to say, it performs identical computations in a lock-step, synchronous fashion over separate data streams. Its computational access to main memory is highly constrained: each of the 64 Processing Units can access directly only a private section of the whole memory. Data can be passed from one Processing Unit to another by a relatively expensive routing instruction. This is executed identically by all Processing Units and passes data a uniform end-around distance in the fixed ordering of the Processing Units. The machine executes most efficiently those computations which are element-by-element operations on vectors or arrays. Thus, the most fruitful sources of parallelism in Fortran programs intended for ILLIAC IV execution are DO loops containing array references with subscripts depending on the DO index variables.