A Scan-Based Lower-Power Testing Architecture for Modern Circuits

Advances in Very-large-scale integration (VLSI) technology enable billions of logic gates to be integrated into a single chip. The rapid development of VLSI technology has created new difficulties for design and test engineers. The power consumption of the test is one of the important issues. This article describes a scanning architecture that enables high-quality and low-power testing by modifying test samples in test applications. When the test sample switches a large number of scan flip-flops in each shift, the stability of the circuit is lowered, the fault verification is difficult, the product yield is reduced, and the life is shortened, which is a serious problem. In the paper structure, part of the displacement power is solved. One method is to reduce the number of toggle triggers and reduce the switching activity caused by the move of test samples. The method calculates the switching activity of the scan trigger during the scan operation. Move to the appropriate scan path in the test sample.