Dynamic Ternary Logic Gate Using Neuron-MOS Literal Circuit and Double Pass-Transistor Logic

A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic(DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality principles for generation of dynamic ternary complementary and dual circuits using double pass-transistor are also presented. The design results of dynamic ternary AND/NAND, OR/NOR, and mod-3 multiplication gate, demonstrate the effectiveness of the proposed scheme. The benefit of the proposed voltage-mode dynamic ternary gates is that they can be fabricated by standard CMOS process with a 2-ploy layer. Besides, they have simple and perfectly symmetrical structure. The effectiveness of the proposed dynamic ternary gates has been validated by HSPICE simulation results with TSMC 0.35µm 2-ploy 4-metal CMOS technology.

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