Assessing and mitigating radiation effects in Xilinx SRAM FPGAs

This work intends to help designers assess and mitigate radiation effects in systems that use SRAM-based FPGAs. Several methodologies combining experimental procedure, mitigation strategies and technical aspects are discussed.

[1]  Luigi Carro,et al.  Designing fault-tolerant techniques for SRAM-based FPGAs , 2004, IEEE Design & Test of Computers.

[2]  Heather M. Quinn,et al.  Terrestrial-based radiation upsets: a cautionary tale , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[3]  C. Carmichael,et al.  Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs) , 2004, IEEE Transactions on Nuclear Science.

[4]  Massimo Violante,et al.  Efficient estimation of SEU effects in SRAM-based FPGAs , 2005, 11th IEEE International On-Line Testing Symposium.

[5]  P. Graham,et al.  Radiation-induced multi-bit upsets in SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[6]  M. Wirthlin,et al.  Improving FPGA Design Robustness with Partial TMR , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[7]  C. Carmichael,et al.  Single Event Upsets in Xilinx Virtex-4 FPGA Devices , 2006, 2006 IEEE Radiation Effects Data Workshop.

[8]  M. Berg,et al.  Fault tolerance implementation within SRAM based FPGA designs based upon the increased level of single event upset susceptibility , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).