Systolic array architecture for two-dimensional deconvolution

Abstract Systolic arrays for one-dimensional convolution and deconvolution have been introduced in the literature. In this paper, a systolic array architecture for two-dimensional deconvolution (2D-DCV) is presented. The systolic array consists of two types of processing cells referred to as inner cells and base cells. Intermediate computation of 2D-DVC are carried out by the inner cells at different stages and passed through the pipeline interconnections to the base cells to compute the required results and deliver them to the output terminals of the systolic array. The design and operation of each type of processing cell will be described. The pipeline interconnections and data flow within the systolic array will be presented too.