Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode. In this paper, existing low leakage SRAM structures are analyzed by several SPEC2000 benchmarks. As expected, the examined SRAM architectures have static power consumption lower than the conventional 6-T SRAM cell. However, the additional activities performed to enter and to exit the sleep mode also lead to higher dynamic energy. Our study demonstrates that, due to this, the overall energy consumption achieved by the known low-leakage techniques is greater than the conventional approach. In the second part of this paper, a novel low-leakage SRAM cell is presented. The proposed structure establishes when to enter and to exit the sleep mode, on the basis of the data stored in it, without introducing time and energy penalties with respect to the conventional 6-T cell. The new SRAM structure was realized using the UMC 0.18-mum, 1.8-V, and the ST 90-nm 1-V CMOS technologies. Tests performed with a set of SPEC2000 benchmarks have shown that the proposed approach is actually energy efficient

[1]  N. Vallepalli,et al.  SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction , 2005, IEEE Journal of Solid-State Circuits.

[2]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[3]  Anantha Chandrakasan,et al.  Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[4]  Norman P. Jouppi,et al.  WRL Research Report 93/5: An Enhanced Access and Cycle Time Model for On-chip Caches , 1994 .

[5]  Kaushik Roy,et al.  A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Trevor Mudge,et al.  The MIRV SimpleScalar/PISA Compiler , 2000 .

[7]  Krste Asanovic,et al.  Dynamic fine-grain leakage reduction using leakage-biased bitlines , 2002, ISCA.

[8]  K. Itoh,et al.  A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[9]  Koji Nii,et al.  A low power SRAM using auto-backgate-controlled MT-CMOS , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[10]  Narayanan Vijaykrishnan,et al.  On load latency in low-power caches , 2003, ISLPED '03.

[11]  Kouichi Kanda,et al.  Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[12]  Margaret Martonosi,et al.  Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.

[13]  David J. Sager,et al.  The microarchitecture of the Pentium 4 processor , 2001 .

[14]  T. Sakurai,et al.  90% write power-saving SRAM using sense-amplifying memory cell , 2004, IEEE Journal of Solid-State Circuits.

[15]  Richard E. Kessler,et al.  The Alpha 21264 microprocessor , 1999, IEEE Micro.

[16]  Hiroshi Kawaguchi,et al.  Dynamic leakage cut-off scheme for low-voltage SRAM's , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[17]  Kaushik Roy,et al.  Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors , 2002, ISLPED '02.

[18]  Kaushik Roy,et al.  A single-Vt low-leakage gated-ground cache for deep submicron , 2003, IEEE J. Solid State Circuits.

[19]  Akhilesh Tyagi,et al.  WARM SRAM: a novel scheme to reduce static leakage energy in SRAM arrays , 2004, IEEE Computer Society Annual Symposium on VLSI.

[20]  K. Ishibashi,et al.  16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[21]  David Blaauw,et al.  Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.

[22]  K. Nii,et al.  A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications , 2004, IEEE Journal of Solid-State Circuits.

[23]  Kiat Seng Yeo,et al.  Low Voltage, Low Power VLSI Subsystems , 2004 .

[24]  K. Osada,et al.  A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme , 2005, IEEE Journal of Solid-State Circuits.

[25]  Dirk Grunwald,et al.  Pipeline gating: speculation control for energy reduction , 1998, ISCA.

[26]  Jan M. Rabaey,et al.  SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).