On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults
暂无分享,去创建一个
[1] Bidyut Gupta,et al. Syndrome Testable Design of Combinational Networks for Detecting Stuck-At and Bridging Faults , 1983, ITC.
[2] Wayne A. Davis,et al. Minimal Fault Tests for Combinational Networks , 1974, IEEE Transactions on Computers.
[3] Dhiraj K. Pradhan,et al. Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets , 1980, IEEE Transactions on Computers.
[4] B. Gupta,et al. Anomalous effect of a stuck-at fault in a combinational logic circuit , 1983, Proceedings of the IEEE.
[5] John P. Hayes,et al. Transition Count Testing of Combinational Logic Circuits , 1976, IEEE Transactions on Computers.
[6] Alfred K. Susskind,et al. Testing by Verifying Walsh Coefficients , 1983, IEEE Transactions on Computers.
[7] SUDHAKAR M. REDDY,et al. Multiple Fault Detection in Combinational Networks , 1972, IEEE Transactions on Computers.
[8] K. S. Ramanatha,et al. A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays , 1983, IEEE Transactions on Computers.
[9] Yves Crouzet,et al. Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.
[10] Premachandran R. Menon,et al. A Practical Approach to Fault Simulation and Test Generation for Bridging Faults , 1985, IEEE Transactions on Computers.
[11] Vinod K. Agarwal,et al. Generic Fault Characterizations for Table Look-Up Coverage Bounding , 1980, IEEE Transactions on Computers.
[12] K. C. Y. Mei,et al. Bridging and Stuck-At Faults , 1974, IEEE Transactions on Computers.
[13] Arunabha Sen,et al. On System Diagnosability in the Presence of Hybrid Faults , 1986, IEEE Transactions on Computers.
[14] James E. Smith. Detection of Faults in Programmable Logic Arrays , 1979, IEEE Transactions on Computers.
[15] Daniel L. Ostapko,et al. Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's) , 1979, IEEE Transactions on Computers.
[16] Stanley L. Hurst. The logical processing of digital signals , 1978 .
[17] Vinod K. Agarwal,et al. Multiple Fault Testing of Large Circuits by Single Fault Test Sets , 1981, IEEE Transactions on Computers.
[18] ALEXANDER IOSUPOVICZ. Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic , 1978, IEEE Transactions on Computers.
[19] Vinod K. Agarwal. Multiple Fault Detection in Programmable Logic Arrays , 1980, IEEE Transactions on Computers.
[20] Francisco J. O. Dias. Fault Masking in Combinational Logic Circuits , 1975, IEEE Transactions on Computers.
[21] Mark G. Karpovsky,et al. Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines , 1980, IEEE Transactions on Computers.
[22] James E. Smith. On Necessary and Sufficient Conditions for Multiple Fault Undetectability , 1979, IEEE Transactions on Computers.
[23] Vinod K. Agarwal,et al. Non-Stuck-At Fault Detection in nMOS Circuits by Region Analysis , 1983, ITC.
[24] John P. Hayes. On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests , 1971, IEEE Transactions on Computers.
[25] Jacob Savir,et al. Syndrome-Testable Design of Combinational Circuits , 1980, IEEE Transactions on Computers.
[26] Bidyut Gupta,et al. Logical Modeling of Physical Failures and Their Inherent Syndrome Testability in MOS LSI/VLSI Networks , 1984, ITC.
[27] Janusz Rajski,et al. Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays , 1985, IEEE Transactions on Computers.
[28] Leon I. Maissel,et al. An Introduction to Array Logic , 1975, IBM J. Res. Dev..
[29] Hideo Fujiwara. On Closedness and Test Complexity of Logic Circuits , 1981, IEEE Transactions on Computers.
[30] Arthur D. Friedman. Diagnosis of Short-Circuit Faults in Combinational Circuits , 1974, IEEE Transactions on Computers.