A novel technique for technology-scalable STT-RAM based L1 instruction cache

STT-RAM is an emerging memory cell to construct on-chip memories or caches. However, in advanced process technology, it is known that STT-RAM cells are vulnerable to read disturbance. To employ STTRAM cells in on-chip caches for better energyand cost-efficiency, appropriate techniques to prevent or avoid read disturbance are essential. In this paper, we propose a novel architectural technique to enable an energyand performance-efficient STT-RAM based L1 instruction caches for future process technologies. Our selective way access with a write line buffer adopts a sequential cache access between the MRU way and non-MRU way, reducing energy overhead from the data restoring after the read operation. In addition, the write line buffer hides a latency of currently pending or on-going write operations in L1 instruction caches, minimizing stalls in processor pipelines. Our proposed techniques improve performance per Watt of the STT-RAM based L1 instruction cache by 1.6X and 2.6X compared to the conventional SRAM-based cache (denoted as SRAM in this paper) and STT-RAM based cache with the naive data restoring (denoted as STTRAM_dr in this paper).

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