VLSI Dynamic nMOS design constraints due to drain induced primary and secondary impact ionization

Evidence of primary and secondary impact ionization have been reported recently in small geometry MOSFETs. We confirm the generation of secondary electrons by the impact ionization of primary holes accelerated through the drain to substrate voltage. A quantitative measure of the secondary electrons that diffuse into bulk is established and diffusion lengths of ∼400-650 µm are measured. This represents a non-thermal leakage source which is a dominant leakage phenomena below ∼60°C. We show that for high temperature operation this mechanism does not degrade dynamic nMOS performance at 3 µm, but could be severe at smaller geometry. This non-thermal process precludes the advantages claimed for a cold FET VLSI technology.