Alleviating routing congestion by combining logic resynthesis and linear placement
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[1] Takao Uehara,et al. Optimal Layout of CMOS Functional Arrays , 1978, 16th Design Automation Conference.
[2] Yang Cai,et al. Minimizing channel density by shifting blocks and terminals , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[3] Robert K. Brayton,et al. Timing optimization of combinational logic , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[4] Ing-Jer Huang,et al. Application-Driven Design Automation for Microprocessor Design , 1992, DAC.
[5] R. M. Mattheyses,et al. A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.
[6] Takeshi Yoshimura,et al. Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] C. L. Liu,et al. Permutation Channel Routing , 1988 .
[8] Min-Siang Lin,et al. Channel density reduction by routing over the cells , 1991, DAC '91.
[9] Massoud Pedram,et al. Layout driven technology mapping , 1991, 28th ACM/IEEE Design Automation Conference.
[10] Jason Cong,et al. Over-the-cell channel routing , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Gabriele Saucier,et al. ASYL: A Rule-Based System for Controller Synthesis , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Robert K. Brayton,et al. Multilevel logic synthesis , 1990, Proc. IEEE.
[13] D. Gregory,et al. SOCRATES: A System for Automatically Synthesizing and Optimizing Combinational Logic , 1986, 23rd ACM/IEEE Design Automation Conference.
[14] Gabriele Saucier,et al. Multilevel synthesis minimizing the routing factor , 1991, DAC '90.
[15] Paul Glick,et al. An Over-The-Cell Router , 1980, 17th Design Automation Conference.
[16] Chi-Ping Hsu,et al. General River Routing Algorithm , 1983, 20th Design Automation Conference Proceedings.
[17] Michael Ian Shamos,et al. Computational geometry: an introduction , 1985 .
[18] K. Keutzer. DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, 24th ACM/IEEE Design Automation Conference.
[19] Richard M. Karp,et al. Minimization Over Boolean Graphs , 1962, IBM J. Res. Dev..
[20] Alberto Sangiovanni-Vincentelli,et al. Logic synthesis for vlsi design , 1989 .
[21] Uehara,et al. Optimal Layout of CMOS Functional Arrays , 1981 .
[22] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[23] I. Pyo,et al. Application-driven design automation for microprocessor design , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[24] Sze-Tsen Hu. ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .
[25] Chak-Kuen Wong,et al. Maximizing pin alignment in semi-custom chip circuit layout , 1988, Integr..
[26] Robert K. Brayton,et al. Delay optimization of combinational logic circuits by clustering and partial collapsing , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.